Measuring the similarity of spike-trains is an essential operation for temporal neural coding, spike-based local learning rules, stereo vision and audio, for matching neuronal responses to their evoking stimuli, or for use as a loss function in supervised learning tasks in spiking neural networks. We present a novel spike-based temporal correlator and its accompanying analog subthreshold VLSI implementation, which can perform this operation accurately and efficiently. We discuss two potential applications of this primitive: (1) In event-based neuromorphic systems, it can be used to correlate spike-trains from multiple sources, e.g. pre- and post-synaptic spikes for spike-timing-dependent analog on-chip learning, or event-streams from multiple sensors like dynamic vision sensors and silicon cochleae for stereo-perception. (2) In (neuromorphic) neural interfaces the same framework can be used to correlate neural tissue activity with event-based stimuli, allowing us to identify the characteristic time-constant of the system, assuming integrative dynamics. We verify our results via schematic simulations in a 180nm process.

Accurately capturing dynamic scenes with wide-ranging motion and light intensity is crucial for many vision applications. However, acquiring high-speed high dynamic range (HDR) video is challenging because the camera's frame rate restricts its dynamic range. Existing methods sacrifice speed to acquire multi-exposure frames. Yet, misaligned motion in these frames can still pose complications for HDR fusion algorithms, resulting in artifacts. Instead of frame-based exposures, we sample the videos using individual pixels at varying exposures and phase offsets. Implemented on a monochrome pixel-wise programmable image sensor, our sampling pattern captures fast motion at a high dynamic range. We then transform pixel-wise outputs into an HDR video using end-to-end learned weights from deep neural networks, achieving high spatiotemporal resolution with minimized motion blurring. We demonstrate aliasing-free HDR video acquisition at 1000 FPS, resolving fast motion under low-light conditions and against bright backgrounds - both challenging conditions for conventional cameras. By combining the versatility of pixel-wise sampling patterns with the strength of deep neural networks at decoding complex scenes, our method greatly enhances the vision system's adaptability and performance in dynamic conditions.

In this paper, we present the implementation of Velocity Controlled (or tuned) Oscillators (VCO) to model spatial coding and navigation in the mammalian hippocampus. Specifically, we demonstrate these spatial cells by representing a spatial firing map of grid, place, and border cells. Since the VCO is the basis for Oscillatory Interference (OI) models based on the Spatial Envelope Synthesis (SES) approach of hippocampal and entorhinal navigation, we use these models in our hardware implementation to construct more complex spatial cells from simple interference between VCOs. We develop the design of a VCO ASIC chip containing up to 128 independently tuned VCOs.

Grid, place, and border cells in the mammalian hippocampus and entorhinal cortex perform highly sophisticated navigational tasks with an extremely low power budget. While previous algorithms for simultaneous localization and mapping (SLAM) in robotics have used these cells for inspiration, they have sacrificed the robust, low-power gains achieved with bioplausible models for ease of implementation. This paper presents steps towards robotic navigation with biologically realistic hippocampal models by implementing velocity-controlled oscillators, a basis for any spatially-tuned neuron, on mixed-mode neuromorphic spiking hardware.

We will demonstrate a real-time implementation of a protoobject based neuromorphic visual saliency model [1] on an embedded processing board. Visual saliency models are difficult to implement in hardware for real-time applications due to their computational complexity. The conventional implementation is not optimal because of the requirement of a large number of convolution operations for filtering on several feature channels across multiple image pyramids. Our current implementation considers the dynamic temporal motion change by convoluting along time efficiently by parallelly processing them. We have implemented the model on an NVIDIA Jetson TX1 board (Fig. 1), which has NVIDIA Maxwell GPU with 256 NVIDIA CUDA Cores, hosted on an Ubuntu environment. The board has a 5 MP fixed focus MIPI CSI camera through which the frames are fetched using a Quad-core ARM Cortex-A57 MPCore Processor with 4 GB LPDDR4 Memory. The camera module fetches the frames to the application for processing, and the result is then displayed through the HDMI port. The application is written in Tensorflow, Cuda, and Python and uses several Python libraries. For further analysis, the user can also save the output onto a file.

One of the problems of real time compressed sensing system is the computational cost of the reconstruction algorithms. It is especially problematic for close loop sensory applications where the sensory parameters needs to be constantly adjust to adapt to a dynamic scene. Through a preliminary experiment with MNIST dataset, we showed that we can extract some scene information (object recognition, scene movement direction and speed) based on the compressed samples using a deep convolutional neural network. It achieves 100% percent accuracy in distinguishing moving velocity, 96.22% in recognizing the digit and 90.04% in detecting moving direction after the code images are re-centered. Even though the classification accuracy drops slightly compared to using original videos, the computational speed is two time faster than classification on videos directly. This method also eliminates the need for sparse reconstruction prior to classification.

This paper proposes a model based approach to the development of a wireless biotelemetry communications system model that enables early architecture trades and optimization for safety, performance and power efficiency. This integrated system model is constructed using a model based engineering framework which enables the digital integration of requirements, architecture and disparate performance models to determine the optimal solution for an implanted communication system. In the conceptual and early design phases of a biotelemetry system one must consider the constraints of implanting devices in humans and animals, as well as those imposed on short range, high data rate wireless communications. This approach considers the effects of radio frequency performance, power dissipation, specific absorption rate (SAR), the implanted environment, propagation channel characteristics, data rates and also the receiver noise figure and sensitivity. The integrated model greatly improves the ability of the designer to quickly analyze hundreds or even thousands of trade studies while considering system requirements. The implementation of this model based framework was completed in 6 steps: requirements analysis and architecture development, identification of key performance parameters, system decomposition into functional building blocks and input/output definitions, analytical model creation, system model creation with models and validated data and finally, trade space simulation, analysis, visualization and optimization.

Summary form only given. The smallest wirelessly powered neural implant to date is demonstrated. Power is sent over a near-field inductive link. The implant system is realized on a single CMOS ASIC which includes the on-chip coil, the harvesting circuit, and the current driver. The entire system is fabricated in a 0.13 μm CMOS process and occupies merely 180 μm × 180 μm.

This work introduces the smallest wirelessly powered neural implant to date. We provide experiment verification by successfully stimulating the sciatic nerve of a rat. Power is deliverd over a 1.7 GHz inductive link at a distance of 0.5 cm. A method is also proposed to generate biphasic current pulses without the use of a controller. The entire system is fabricated in a 0.13 μm CMOS process and occupies merely 180 μm × 180 μm.

Iontophoresis and electroporation are two progressively expanding methods that are used to enhance drug delivery into the human body. They involve the exposure of cells to an external electric field, to drive genetic drugs (plasmid) to a desired location or permeabilize the cell's membranes for the drug to pass. While electroporation has been successful in enhancing plasmid gene therapy in the past, it requires very high local voltages and is less suitable for treating large wounds. Iontophoresis refers to the application of a controlled current at typically lower voltages and is of great interest for clinical wound healing involving naked plasmid transfection. We propose an electrical stimulation setup and instrumentation for meeting the demands of this advancing field. Extensive simulations of electrode placements on rat skin models are performed in COMSOL to determine the most promising setup for in vivo iontophoresis. Electrical circuits for iontophoresis, as well as for the measurement of resulting electrical parameters, are designed, simulated, built and tested. Finally, iontophoresis is performed in vivo (on rat dorsum) using intradermally injected DNA plasmids.

Neuromorphic systems mimic the functionality and communication protocol of biological neurons with efforts to design the most size and power efficient computing systems. We demonstrate the capability of an in-house neural array of 4080 Mihalas-Niebur neurons designed in 0.5μm CMOS technology to perform various event-based image processing tasks including warping and filtering.

We present an array of Mihalas-Niebur neurons with dynamically reconfigurable synapses implemented in 0.5 μm CMOS technology optimized for low-power, low-mismatch, and high-density. This neural array has two modes of operation: one is each cell in the array operates as independent leaky integrate-and-fire neurons, and the second is two cells work together to model the Mihalas-Niebur neuron dynamics. Depending on the mode of operation, this implementation consists of 2040 Mihalas-Niebur neurons or 4080 I&F neurons within a 3mm χ 3mm area. Each I&F neuron cell consumes an area of 1495μm2 and the neural array dissipates 360pJ of energy per synaptic event measured at 5.0V power supply (∼14pJ at 1.0V estimated from SPICE simulation).

Autonomous aerial vehicles perofrming visual tasks must operate under low-power, small-size, and light-weight constraints. We demonstrate an event-based dewarping task using a neuromorphic camera and processor for efficiently performing this visual task for a mobile quadcopter in real-time.

We demonstrate dynamic visual saliency computation within a virtual environment using the Oculus Rift with a custom eye tracker. The visual display is representative of the real-time view of a mobile robot with two mounted first-person view cameras for stereoscopic vision.

Visual saliency models are difficult to implement in hardware for real time applications due to their computational complexity. The conventional digital implementation is not optimal because of the requirement of a large number of convolution operations for filtering on several feature channels across multiple image pyramids [1], [2]. Here, we propose an alternative approach to implement a neuromorphic visual saliency algorithm [3] in digital hardware using stochastic computation, which can achieve very low power and small area. We show the real time implementation of important building blocks of the system and compare the overall system with its software implementation. Our implementation will be useful for facilitating high-fidelity selective rendering in computer graphics applications using the output of the saliency model, and for communications, where the non-salient parts of an image can be compressed more heavily than the salient parts. Our implementation will find several applications as a frontend co-processor for information triaging, compression and analysis in computer vision tasks. Our proposed SC-based convolution circuit could be a potential building block for implanting deep convolutional neural networks (CNN) on hardware.

A compact all-CMOS spatiotemporal compressed sensing (CS) video camera is demonstrated. This CS-based framework [1], implemented on integrated circuits, is able to achieve 20-fold reduction in the readout speed and consumes only 14μW to provide 100 fps videos. Taking advantage of dictionary learning and sparse recovery, this prototype image sensor (127×90 pixels) can reconstruct 100 fps videos from the coded images sampled at 5 fps.

This paper describes a miniaturized inductively powered neural stimulator chip. We propose a solution to overcome the bulkiness of present neural implants by eliminating the need for data decoders, digital control blocks and clocks. This approach trades-off programmability, such as precise stimulus amplitude control, for a considerable reduction in chip area and power consumption. The system is fabricated in a 0.18 μm CMOS process, consumes about 16 μW and occupies merely 220 μm × 180 μm.

There is increasing interest for aerial vehicles to perform image processing tasks (i.e. object recognition and detection) in real-time. Such systems systems should have minimal data throughput, low computational complexity, and low-power. Traditional frame-based digital cameras are not ideal for meeting such specifications. More recent cameras, inspired by biology, drastically reduce data throughput by representing information in event streams, and in doing so, represent image information temporally. In this work, we utilize the ATIS (Asynchronous Time-based Image Sensor) in conjunction with a Field-Programmable Gate Array implementation of the Integrate-and-Fire Array Transceiver for performing an event-based, simultaneous image dewarping and filtering task. The ATIS output is inherently event-based and stochastic, giving our system the low data throughput and low-power specifications that we seek, as it more directly mimics the communication protocol of biological neurons. We further emphasize how our system can be coupled with aerial vehicles that must perform visual tasks in real-time on a coherent representation of what its camera has captured.

To meet the growing demand of wireless and power efficient neural recordings systems, we demonstrate an unsupervised dictionary learning algorithm in Compressed Sensing (CS) framework which can be implemented in VLSI systems. Without prior label information of neural spikes, we extend our previous work to unsupervised learning and construct a dictionary with discriminative structures for spike sorting. To further improve the reconstruction and classification performance, we proposed a joint prediction to determine the class of neural spikes in dictionary learning. When the neural spikes is compressed 50 times, our approach can achieve an average gain of 2 dB and 15 percentage units over state-of-the-art of CS approaches in terms of the reconstruction quality and classification accuracy respectively.

This paper introduces a spiking hierarchical model for object recognition which utilizes the precise timing information inherently present in the output of biologically inspired asynchronous address event representation (AER) vision sensors. The asynchronous nature of these systems frees computation and communication from the rigid predetermined timing enforced by system clocks in conventional systems. Freedom from rigid timing constraints opens the possibility of using true timing to our advantage in computation. We show not only how timing can be used in object recognition, but also how it can in fact simplify computation. Specifically, we rely on a simple temporal-winner-take-all rather than more computationally intensive synchronous operations typically used in biologically inspired neural networks for object recognition. This approach to visual computation represents a major paradigm shift from conventional clocked systems and can find application in other sensory modalities and computational tasks. We showcase effectiveness of the approach by achieving the highest reported accuracy to date (97.5% ± 3.5%) for a previously published four class card pip recognition task and an accuracy of 84.9% ± 1.9% for a new more difficult 36 class character recognition task.

The articles in this special issue focus on applications supported by bioinspired image processing.

Visual motion estimation is a computationally intensive, but important task for sighted animals. Replicating the robustness and efficiency of biological visual motion estimation in artificial systems would significantly enhance the capabilities of future robotic agents. Twenty five years ago, in this very journal, Carver Mead outlined his argument for replicating biological processing in silicon circuits. His vision served as the foundation for the field of neuromorphic engineering, which has experienced a rapid growth in interest over recent years as the ideas and technologies mature. Replicating biological visual sensing was one of the first tasks attempted in the neuromorphic field. In this paper, we focus specifically on the task of visual motion estimation. We describe the task itself, present the progression of works from the early first attempts through to the modern day state-of-the-art, and provide an outlook for future directions in the field.

High quality CMOS image sensors are of great importance for LoC - Lab-on-Chip devices based on optical measurements. The main target in these devices is to minimize the cost and area while achieving a good resolution. The performance parameters of image sensor pixels and CMOS compatible photodiodes depend on the size, type and the geometry of the photodiode layout and varies for each technology. In this study, we present a comparative analysis of CMOS compatible photodiode types at different areas. The results have shown n-well/p-sub type photodiode with 5×5 μm2diffusion area achieves the highest sensitivity (69.81 × 1012V.s-1.cm-2/W.cm-2) and with 40 × 40 μm2diffusion area, highest SNR - Signal-to-Noise Ratio (72.26dB) at 630 nm, while the p+/n-well/p-sub type photodiode with 40 × 40 μm2diffusion area results in highest responsivity (0.466 A. cm-2/W.cm-2) at the same wavelength.

We demonstrate a method to build signal dependent sparse representation dictionary for neural action potentials using K-SVD algorithm and Discrete Wavelets Transform. We also show a method to utilize this dictionary to recover the neural signal in the Compressive Sensing (CS) framework. Comparing against the non-signal dependent CS recovery algorithms, this new recovery algorithm can achieve same reconstruction quality with 2.5 times less compressed sensing measurements. For the same compression ratio, the purposed approach can increase recovery signal's signal to noise and distortion ratio (SNDR) by around 6 dB compare to non-signal dependent recovery method. We also evaluated the recovered signal using spike sorting techniques. The results have shown that the spikes clusters still maintain clear separation even when the compression ratio is at 15-20% of the Nyquist rate. This work also implies that any hardware implementation of compressed sensing could be scaled down in term of power and chip area by the same order if this signal dependent framework is used to recover the signal.

Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects that are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application.

Spiking neuron models are used in a multitude of tasks ranging from understanding neural behavior at its most basic level to neuroprosthetics. The desired neural output is achieved through the use of complex neural models with multiple parameters which need to be tuned - a time consuming and difficult task. Silicon provides an attractive medium in which to implement these models. However due to fabrication imperfections the task of parameter configuration becomes even more complex. We show how a Maximum Likelihood method can be applied to a leaky integrate and fire silicon neuron with spike induced currents to fit the neurons output to desired spike times. On average the interspike intervals of the predicted spike times match the desired interspike intervals to within 4% of the desired interspike interval.

When a neuronal spike train is observed, what can we deduce from it about the properties of the neuron that generated it? A natural way to answer this question is to make an assumption about the type of neuron, select an appropriate model for this type, and then choose the model parameters as those that are most likely to generate the observed spike train. This is the maximum likelihood method. If the neuron obeys simple integrate-and-fire dynamics, Paninski, Pillow, and Simoncelli (2004) showed that its negative log-likelihood function is convex and that, at least in principle, its unique global minimum can thus be found by gradient descent techniques. Many biological neurons are, however, known to generate a richer repertoire of spiking behaviors than can be explained in a simple integrate-and-fire model. For instance, such a model retains only an implicit (through spike-induced currents), not an explicit, memory of its input; an example of a physiological situation that cannot be explained is the absence of firing if the input current is increased very slowly. Therefore, we use an expanded model (Mihalas & Niebur, 2009 ), which is capable of generating a large number of complex firing patterns while still being linear. Linearity is important because it maintains the distribution of the random variables and still allows maximum likelihood methods to be used. In this study, we show that although convexity of the negative log-likelihood function is not guaranteed for this model, the minimum of this function yields a good estimate for the model parameters, in particular if the noise level is treated as a free parameter. Furthermore, we show that a nonlinear function minimization method (r-algorithm with space dilation) usually reaches the global minimum.

There are a number of spiking and bursting neuron models with varying levels of complexity, ranging from the simple integrate-and-fire model to the more complex Hodgkin-Huxley model. The simpler models tend to be easily implemented in silicon but yet not biologically plausible. Conversely, the more complex models tend to occupy a large area although they are more biologically plausible. In this paper, we present the 0.5 μm complementary metal-oxide-semiconductor (CMOS) implementation of the Mihalaş-Niebur neuron model--a generalized model of the leaky integrate-and-fire neuron with adaptive threshold--that is able to produce most of the known spiking and bursting patterns that have been observed in biology. Our implementation modifies the original proposed model, making it more amenable to CMOS implementation and more biologically plausible. All but one of the spiking properties--tonic spiking, class 1 spiking, phasic spiking, hyperpolarized spiking, rebound spiking, spike frequency adaptation, accommodation, threshold variability, integrator and input bistability--are demonstrated in this model.

We present a series of circuits for implementing silicon synapses with biologically plausible temporal dynamics and independent global control over gain and time-constant. These types of circuits are useful for implementing synaptic dynamics in neuromorphic networks of spiking neurons, and adaptive or homeostatic mechanisms for controlling the synaptic weights. We demonstrate very compact circuit solutions, with as few as six transistors, that can be used as synaptic elements which behave like linear-integrators. The integrators are designed with translinear loops and provide an intuitive and flexible synthesis methodology.

Spiking neurons and spiking neural circuits are finding uses in a multitude of tasks such as robotic locomotion control, neuroprosthetics, visual sensory processing, and audition. The desired neural output is achieved through the use of complex neuron models, or by combining multiple simple neurons into a network. In either case, a means for configuring the neuron or neural circuit is required. Manual manipulation of parameters is both time consuming and non-intuitive due to the nonlinear relationship between parameters and the neuron's output. The complexity rises even further as the neurons are networked and the systems often become mathematically intractable. In large circuits, the desired behavior and timing of action potential trains may be known but the timing of the individual action potentials is unknown and unimportant, whereas in single neuron systems the timing of individual action potentials is critical. In this paper, we automate the process of finding parameters. To configure a single neuron we derive a maximum likelihood method for configuring a neuron model, specifically the Mihalas-Niebur Neuron. Similarly, to configure neural circuits, we show how we use genetic algorithms (GAs) to configure parameters for a network of simple integrate and fire with adaptation neurons. The GA approach is demonstrated both in software simulation and hardware implementation on a reconfigurable custom very large scale integration chip.

In this paper we present the circuits and simulation results for a silicon neuron which is based on a modified version of the Mihalas-Niebur neural model [1]. This silicon neuron produces 15 of the 20 known neural spiking and bursting behaviors. It has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems. Implemented in a 0.15um 1.5V CMOS process, each neuron consumes about 7.5nW of power at 1kHz and occupies an area of 70um by 70um.

With the advent of miniaturised sensors for various engineering and medical applications there is an increased demand of low-power, low-voltage analog building blocks like opamps and OTAs. Degradation of certain amplifier characteristics with supply voltage is a major concern for low-voltage design and often poses contradictory requirement. CMRR (common mode rejection ratio), one such feature, is essential for sensing small bio-electric signals riding over large common-mode voltage. Here we focus on the challenging task of building a low-voltage OTA with high CMRR along with wide CMR (common mode range) and high output impedance. Robust tail current sources for a complementary differential pair OTA with folded cascode output is implemented for the purpose. The circuits are designed and simulated in 0.35 mum standard CMOS technology with supply voltage of 1.8 V. We could demonstrate a maximum of upto 40 dB increase in CMRR for a range of common-mode voltages.

We present a first-order nonhomogeneous Markov model for the interspike-interval density of a continuously stimulated spiking neuron. The model allows the conditional interspike-interval density and the stationary interspike-interval density to be expressed as products of two separate functions, one of which describes only the neuron characteristics and the other of which describes only the signal characteristics. The approximation shows particularly clearly that signal autocorrelations and cross-correlations arise as natural features of the interspike-interval density and are particularly clear for small signals and moderate noise. We show that this model simplifies the design of spiking neuron cross-correlation systems and describe a four-neuron mutual inhibition network that generates a cross-correlation output for two input signals.

An image sensor with focal plane based hardware acceleration of video compression is presented. The 90 x 90 pixel CMOS image sensor provides in-pixel professing of intensity changes, serving as an analog memory and processor for temporal image difference computation. Surveillance quality videos of up to a 48:1 compression ratio via a temporally compensated DCT based compression algorithm is attained with just an 18.5 MHz micro-controller. Power consumption is 225 mW during full operation and 6mVV during full sleep mode that continuously monitors for change events to trigger encoding.

Tissue characterization using ultrasound scattering has been routinely used to extract the cellular properties of tissue. Ultrasonic backscattered radio frequency (RF) data is analyzed to provide estimates of the size, shape and concentration of a wide range of tissues. These tissue parameters form a feature space that can be used to discriminate between tissue types as well as indicate the presence of disease. In this work we develop numerical finite element models of tissue by using spectrum analysis to extract the acoustic properties of three distinct tissue-mimicking phantoms. The tissue-mimicking phantoms are constructed using glass microspheres of diameters 15-45 mum, 40-70 mum and 90-150 mum, embedded in a uniform concentration of gelatin derived from porcine skin. Spectrum analysis of the backscattered data from the tissue phantoms yields acoustic properties (of scatterer size, shape and distribution) which are used to create finite element models (FEM) of the tissue phantom. Simulations of acoustic scattering from an FEM phantom consisting 40 mum scatterers located in a transducer resolution cell is performed. Spectral analysis of the backscattered from the FEM phantom yields an estimate of the scatterer size of 36.7 mum giving an accuracy of 91%.

The cross-correlation function is an important yet computationally intensive processing step in many engineering applications such as wireless communication and object recognition. A neuromorphic approach to this function has been shown to facilitate implementation using a neural-based architecture. Using a custom designed array of silicon neurons on a compact, low-power chip, we demonstrate a cross-correlation system based on two half center oscillators. These preliminary results show the validity of this approach and could provide an elegant solution to wireless communication systems in the next generation of neuroprosthetic devices.

There are various neuron models which can be used to emulate the neural networks responsible for cortical and spinal processes. One example is the Central Pattern Generator (CPG) networks, which are spinal neural circuits responsible for controlling the timing of periodic systems in vertebrates. In order to model the CPG effectively, it is necessary to model not just multiple individual neurons, but also the interactions between them. Due to the complexity of these types of systems, CPG models typically require large numbers (> 10) of parameters making them difficult to understand and control. Genetic Algorithms (GAs) provide a means for optimizing systems with many parameters. We present an automated method that uses a GA to And sets of parameters for a silicon implementation of a neural network capable of producing CPG type signals. This methodology can be used to configure large silicon neural circuits. In this work, constructed networks involving an 18-parameter space, can be used for controlling legged robots and neuroprosthetic devices.

We describe a circuit of two spiking neurons which extracts mathematically accurate cross-correlations from the signal inputs. It differs from prior circuits such as coincidence detectors or enhanced motion detectors in that it does not require anapriorifixed delay between input signals to be selected. The output, in the form of a differential spike histogram, displays a mathematical cross-correlation in the conventional correlation vs. time form.

Video compression algorithms almost universally rely on block matching algorithms (BMA) to exploit the temporal redundancy in image sequences. However block matching is extremely computationally intensive, especially if sub-pixel accuracy is desired. We propose a fundamentally different approach to obtaining motion vectors using the principles from gradient based optical flow but in a form fully compatible with any macro-block based video compression scheme. Experimental results show that in many cases, the gradient approximation to block matching results in videos within 0.3 dB PSNR to BMA at sub-pixel resolution while being potentially much more computationally efficient and easier to implement at the hardware level.

An ultra low power, low bandwidth wireless video sensor network is presented. Each wireless node includes a 90 by 90 CMOS image sensor node with focal plane temporal intensity change detection. As output, the camera provides not only the image intensity, but a digital flag indicating the presence and direction of change, thereby resulting in significant reductions in the amount of external memory and processing power necessary required for operation. Several compression schemes have been developed that take advantage of the change difference signaling from a pixel update wake up mode to a full motion DCT macroblock based scheme. Under typical surveillance scenarios, the temporal change encoding provides up to a twenty fold compression. The sensors have been successfully integrated with a ad-hoc wireless networking system.

The design of a tool-tip mounted cMUT (capacitive micromachined ultrasonic transducer) micro-array for near field imaging of the retina is undertaken. For intra-vitreal applications, a uniformly excited N×N transducer array is limited to a size of 2mm × 2mm. The physical parameters of the array are constrained by the imaging requirements of a 2 μm resolution and a distance of 400 μm from the retinal surface. The mechanical and electrical parameters of the cMUT are calculated using a combination of the Mason equivalent circuit model and finite element techniques. Optimal transmit power and receive sensitivity for this imaging application are obtained by coupling the transducer model to a pseudo-spectral wave propagation model. The pseudo-spectral method is used to calculate the frequency dependent attenuation of the transmitted acoustic pulse through the vitreous and retinal media. The subsequent reflected wavefront is used to optimize the array transmit power and sensitivity.

This paper presents an incremental optical encoder based position and velocity measurements VLSI chip with a serial peripheral interface (SPI). It combines period and frequency countings to provide velocity estimates with good dynamic behavior over a wide speed range. By sensing the velocity of the encoder, it reserves the computational power of a supervisory microcontroller, and subsequently enhances the performance of the total system. Furthermore, multiple copies of the velocity encoder can access the behavior of multiple motors in parallel. It is compact with lower power consumption compared to traditional FPGA implementations. Although designed for use in the control unit of a medical robot with 34-axes and tight space and power constraints, it can be readily used in other applications. It is implemented in a 2P3M0.5μmCMOS process and consumes 4.82mW power with active area of0.45mm2.

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). The event information in an AER system is transferred using a high-speed digital parallel bus. This paper presents an experiment using AER for sensing, processing and finally actuating a robot. The AER output of a silicon cochlea is processed by an AER filter implemented on a FPGA to produce rhythmic walking in a humanoid robot (Redbot). We have implemented both the AER rhythm detector and the central pattern generator (CPG) on a Spartan II FPGA which is part of a USB-AER platform developed by some of the authors

A novel current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is 0.35% of the saturated current. A discussion on theoretical temporal noise limitations of this design is also presented.

In limbed animals, spinal neural circuits responsible for controlling muscular activities during walking are called central pattern generators (CPG). CPG networks display oscillatory activities that actuates individual or groups of muscles in a coordinated fashion so that the limbs of the animal are flexed and extended at the appropriate time and with the required velocity for the animal to efficiently traverse various types of terrain, and to recover from environmental perturbation. Typically, the CPG networks are constructed with many neurons, each of which has a number of control parameters. As the number of muscles increases, it is often impossible to manually, albeit intelligently, select the network parameters for a particular movement. Furthermore, it is virtually impossible to reconfigure the parameters on-line. This paper describes how genetic algorithms (GA) can be used for on-line (re)configuring of CPG networks for a bipedal robot. We show that the neuron parameters and connection weights/network topology of a canonical walking network can be reconfigured within a few of generations of the GA. The networks, constructed with integrate-and-fire-with-adaptation (IFA) neurons, are implemented with a microcontroller and can be reconfigured to vary walking speed from 0.5Hz to 3.5Hz. The phase relationship between the hips and knees can be arbitrarily set (to within 1 degree) and prescribed complex joint angle profiles are realized. This is a powerful approach to generating complex muscle synergies for robots with multiple joints and distributed actuators.

The paper presents an electronic circuit that produces a cross-correlation function for pairs of input signals, without explicitly performing a mathematical algorithm. The circuit uses noisy integrate-and-fire neurons to produce autocorrelation information. Cross-correlation terms are generated by summing a reference signal with the incoming unknown signal. The authors show that the system is capable of extracting the cross-correlation components, and therefore the range information, in the pseudorandom gold codes used to provide ranging signals in the global positioning system (GPS). The circuit is constructed using low power discrete analog electronics, and hence offers the potential for a reduction in GPS receiver power consumption.

We study the dynamic control of ongoing loco-motor patterns through the application of discrete pulses of electrical stimulation to the central pattern generator (CPG) for locomotion. Data is presented from a hardware model of the CPG demonstrating that stimulation causes brief deviations from the CPG's limit cycle activity. It has been shown that the characteristics of the deviation depend strongly on the phase of stimulation. This paper expands upon those previous results in two ways. Firstly, we provide a more detailed characterization of the limit cycle oscillators (LCOs) with the intent of resolving possible asymmetries. Secondly, we use sensory information from a biped robot's "limbs" to set the appropriate timing for the discrete pulse to correct the asymmetries, making it possible to take the computer out of the loop in the generation of the stimulus. Eventually, we believe this approach could lead to development of a neuroprosthetic device for restoring locomotion after paralysis or amputation.

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

An array of 90 /spl times/ 90 active pixel sensors (APS) that performs both in-pixel temporal intensity change detection and analog-to-digital conversion is presented. The 6-T 3-C 25/spl mu/m /spl times/ 25/spl mu/m pixel fabricated on a 0.5/spl mu/m 3M2P CMOS process provides a digital output of light intensity via an integrated single slope ADC. Using the programmable threshold of the pixel level comparator, the imager acquires two exposure levels of a scene simultaneously for increased dynamic range. The imager is intended for surveillance network applications requiring low cost, power efficient sensors remotely operating over bandwidth constrained networks.

Architecture and design parameters for a customizable VLSI chip to control a 34-axis robotic system are presented. The robot, which will be used in throat surgery, includes three small snake-like mechanisms, which places tough design challenges on the controller because of their requirement for precise sensing and control of low motor currents. The chip, in concert with control algorithms executed on a supervisory microprocessor, will deliver the appropriate control voltages to the motor to guide the end-effectors of the robot, while compensating for changes in resistance to motion as the robot interacts with tissue. The chip provides estimates of position, torque and velocity measurements to the microprocessor through a digital interface. Control signals, both generated on-chip and from the microprocessor, are conditioned and presented to the motor driver. The digital interface allows the chip to be configured for different motor specifications and various environmental conditions. Though designed for this particular robot, the chip can be applied to other robots with small DC brush motors

An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image.

This paper presents a two-dimensional programmable normal optical flow measurement chip implemented in 0.5mum CMOS process. The chip is composed of an array of 120times80 APS pixels. The processing circuitry at the periphery of this array computes partial derivatives with respect to space and time and uses them to calculate the normal flow. The spatial derivatives can be programmed to implement 5times5, 3times3 or 1times3 kernels to control the degree of smoothness of the derivatives. The chip occupies an area of 9 mm2and consumes 34.5 mW power (Vdd= 5V). The operation of the chip is demonstrated by first presenting results from individual blocks and then from system-level testing

A second-generation stereo vision chip, fabricated in a 0.35mum 4M2P CMOS process and incorporating two 128 times 128 pixel linear current-mode imagers and current-mode disparity computation circuitry, is presented. Parallel computation of the sum-of-absolute-difference matching metric allows the chip to produce 114 times 124 pixel depth maps at 30 frames per second, performing 2.2 billion operations per second, while using 10.1mA from a 3.3V supply

A new central pattern generator chip with 24 silicon neurons and reprogrammable connectivity is presented. The 3mm /spl times/ 3mm chip fabricated in a 3M2P 0.5/spl mu/m process contains 1032 synapses, each with multiple floating gates for storing parameters governing synaptic strength and polarity. Every neuron includes a dendritic compartment with 12 externally-addressable synaptic inputs and 24 recurrent synaptic inputs, enabling construction of a fully-interconnected network with sensory feedback from off-chip elements. In addition to describing the chip architecture and neuron circuits, preliminary results from single oscillating neurons and pairs of phase-locked neurons are shown. This work represents the realization of a design presented at ISCAS'05, and an improvement over our 2nd generation CPG chip presented at ISCAS'04.

We show that an ongoing locomotor pattern can be modulated by application of discrete electrical stimuli to the spinal cord at specific phases of the locomotor cycle. Data is presented from a series of experiments on in vitro lamprey spinal cords, which were used as an animal model for severe spinal cord injury. For any given stimulus, the effects on frequency, length, and symmetry of locomotor output show a strong dependence on the phase at which stimulation is applied. The most significant changes are seen when stimulation occurs during motor bursting: stimuli applied to the ipsilateral spinal hemicord increase the burst length, while stimuli applied to the contralateral spinal hemicord decrease the burst length. Simulations using experimentally-measured phase-dependent responses indicate that by monitoring the state of the neural system, it should be possible to apply stimuli at the appropriate times to modulate the lamprey "gait" on a cycle-by-cycle basis. Eventually, this approach could lead to development of a neuroprosthetic device for restoring locomotion after paralysis.

We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordinating pattern for locomotion. This network then inhibits an eight-neuron network used to drive patterned movement. We show that we can get predictable control of important relationships such as the phase of the hip and the knee by adjusting tonic parameters. We demonstrate the basic concept both in a simulation that is used to drive a trotting bipedal robot as well as an aVLSI CPG chip that generates spiking burst patterns. Our results indicate that an inhibitory framework can generate simple, understandable and flexible networks for legged robot control that can be implemented in custom VLSI circuits.

We have constructed a system that uses an array of 9,600 spiking sili- con neurons, a fast microcontroller, and digital memory, to implement a reconfigurable network of integrate-and-fire neurons. The system is designed for rapid prototyping of spiking neural networks that require high-throughput communication with external address-event hardware. Arbitrary network topologies can be implemented by selectively rout- ing address-events to specific internal or external targets according to a memory-based projective field mapping. The utility and versatility of the system is demonstrated by configuring it as a three-stage network that accepts input from an address-event imager, detects salient regions of the image, and performs spatial acuity modulation around a high-resolution fovea that is centered on the location of highest salience.

We have constructed a second generation CPG chip capable of generating the necessary timing to control the leg of a walking machine. We demonstrate improvements over a previous chip by moving toward a significantly more versatile device. This includes a larger number of silicon neurons, more sophisticated neurons including voltage dependent charging and relative and absolute refractory periods, and enhanced programmability of neural networks. This chip builds on the basic results achieved on a previous chip and expands its versatility to get closer to a self-contained locomotion controller for walking robots. 1

The locomotor controller for walking, running, swimming, and flying animals is based on a central pattern generator (CPG). Models of CPGs as systems of coupled nonlinear oscillators have been proposed and have been used for the control of robots. In this paper we describe the implementation of an adaptive CPG model in a compact, custom analog VLSI circuit. We demonstrate the function of the chip by controlling an underactuated, running robotic leg. This circuit has adaptive properties that allow it to tune its behavior based on sensory feedback. To our knowledge this is the first instance of an adaptive CPG chip. This approach supports the construction of extremely inexpensive, low power and compact controllers for walking, flying and swimming machines.

An 86(H)/spl times/75(V) Active Pixel Sensor (APS) using a single-capacitor-single-contact pixel, in a BiCMOS process, is presented. The cell size is 14/spl lambda//spl times/14/spl lambda/, using MOSIS' SCMOS design rules. A smaller cell size is possible in non-scalable processes. The pixel is composed of an NPN phototransistor with a floating base; the base is capacitively coupled to the column select line. A large fill factor, for a CMOS APS, of 76.5% is obtained. With an integration time of 27.68 /spl mu/s, pixel sensitivity is 6.2 nA/lux and does not saturate above 8 K lux. The reset scheme provides simultaneous lag and blooming protection at 75 frames/s.

A 16/spl times/16 pixel pseudo general-purpose vision chip for spatiotemporal focal-plane processing is presented. The convolution of the image with programmable kernels are realized with area-efficient and real-time circuits. The chip's architecture allows the photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low power consumption at high computation rates.

A prototype programmable analog neural computer and selected applications are described. The machine is assembled from over 100 custom VLSI modules containing neurons, synapses, routing switches and programmable synaptic time constants. Connection symmetry and modular construction allow expansion to arbitrary size. The network runs in real time analog mode, however connection architecture as well as neuron and synapse parameters are controlled by a digital host that monitors also the network performance through an A/D interface. Programming and monitoring software has been developed and several application examples including the dynamic decomposition of acoustical patterns are described. The machine is intended for real time, real world computations including ATR. In current configuration its maximal speed is equivalent to that of a digital machine capable of more than 1011 flops. A much larger machine is currently under development.