Traditionally, on-chip odometers have been utilized to monitor circuit aging for characterization or mitigation. However, modern applications, such as anticounterfeiting, demand odometers that not only track degradation but also accurately assess the circuit’s actual usage time and operating conditions. To meet these demands, the exploiting of the differing dynamics of key physical degradation mechanisms has been proposed. Unlike existing solutions, which require separate circuits for each degradation mechanism, this paper presents a more efficient approach. We introduce a novel ring oscillator-based odometer that takes advantage of the asymmetric stress of multiple degradation mechanisms. Central to this innovation is a newly developed processing block, the duty cycle-dependent frequency divider. This design enables the circuit to infer degradation data from two distinct mechanisms, positioning it as an ideal solution to monitor circuit usage over time.

Bias Temperature Instability (BTI) poses a significant challenge in ensuring the reliability of digital systems, affecting the delay of digital logic gates, which ultimately can lead into timing failures. Sophisticated defect-centric models have been developed and successfully calibrated against empirical data to forecast the impacts of BTI at the device level. However, their application to large-scale digital circuits operating under realistic workloads over typical system lifetimes is limited because of the computational complexity of defect-centric models. To make the application of aging models in that context feasible, a useful technique is to compress the transistor workloads into simplified and hence manageable representative workloads. While fast in terms of execution speed, previous techniques struggle with accuracy when predicting aging degradation, and can reach a very high average error in threshold voltage increase prediction. In this work, we review the compression techniques described in the literature and propose two novel approaches that surpass existing ones in terms of accuracy, which is demonstrated for a complex digital design used as benchmark. Specifically, our best compression technique matches the predictions obtained through the reference uncompressed workloads, introducing negligible error, and maintains low execution times to efficiently and accurately scale defect-centric models to the circuit level.

Silicon Physical Unclonable Functions (PUFs) have emerged as a promising solution for generating cryptographic keys in low-cost resource-constrained devices. A PUF is expected to be reliable, meaning that its response bits should remain consistent each time the corresponding challenges are queried. Unfortunately, the stability of these challenge-response pairs (CRPs) can be seriously eroded by environmental factors like temperature variations and the aging of the integrated circuits implementing the PUF. Several approaches, including bit masking, bit selection techniques, and error-correcting codes, have been proposed to obtain a reliable PUF operation in the face of temperature variations. As for aging, a new kind of aging-resilient silicon PUF has been reported that uses the time-varying phenomenon known as Random Telegraph Noise (RTN) as the underlying entropy source. Although this type of PUF preserves its reliability well when aged, it is not immune to the impact of temperature variations. The work presented here shows that it is possible to improve the thermal reliability of RTN-based PUFs with a proper combination of (a) a novel optimization-based bit selection technique, that is also applicable to other types of PUFs based on differential measurements; and (b) a temperature-aware tuning of the entropy-harvesting function.

PUFs have emerged as an alternative to traditional Non-Volatile Memories in the field of hardware security. In this paper, a novel PUF is proposed that uses the Random Telegraph Noise phenomenon as the underlying source of entropy. This phenomenon manifests as discrete and random shifts in the drain current of transistors and it is characterized by several parameters like the number of the defects in the device, as well as the emission and capture time constants and current shifts of these defects. Using the recently reported Maximum Current Fluctuation metric, it is possible to condense all this information and use it for the PUF design. By forming pairs of transistors, measuring, and comparing their Maximum Current Fluctuation over a given time interval, we demonstrate using numerical experiments that it is possible to obtain a PUF. Furthermore, the results reported here show that this RTN-based PUF matches, and even out-performs, other silicon PUFs in terms of uniqueness, unpredictability, and reliability with an evident advantage in silicon area.

A new strategy for millimeter-wave (mm-Wave) circuit and system synthesis, where the accuracy of electromagnetic simulations can be achieved in optimization-based design methodologies without sacrificing efficiency, is presented and tested within a real industrial project. This is done by properly partitioning the system, generating libraries of passive devices which are electromagnetically simulated prior to any circuit optimization, generating performance tradeoffs at different hierarchical levels with multiobjective optimization algorithms and hierarchically composing lower level sub-blocks. With this proposed solution, an entire mm-Wave system, from the passive component level up to the system level, has been designed and compared with the results obtained from a conventional design approach, demonstrating the outstanding capabilities of the methodology.

In recent years there has been a growing interest in electronic design automation methodologies for the optimization-based design of radio frequency (RF) circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle RF systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this paper, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multiobjective optimization algorithms are used to design an entire RF system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometer-scale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and time-efficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.

This paper describes a class of real-life optimization problems that has not been addressed before: a multi-objective optimization in which one objective is neither minimized nor maximized but uniformly swept over a wide range. The limitations of conventional multi-objective optimization algorithms to deal with this kind of problems are illustrated via the optimization of radiofrequency inductors. For the first time, an algorithm is proposed that provides sets of solutions for this kind of problems.

Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. The models for the wear-out phenomena typically use the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occur while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower CPU times.

A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a singleobjective and a multiobjective optimization of a low noise amplifier.

The accuracy of high-frequency models of passive RF devices, e.g., inductors or transformers, presents one of the most challenging problems for RF integrated circuits. Accuracy limitations lead RF designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. The first one is based on the segmented model approach, in which each device segment is characterized with a lumped element model. The second technique is based on the generation of surrogate models from the electromagnetic simulation of a set of device samples. Different modeling strategies (frequency separation, filtering according to self-resonance frequency, etc.) will be considered. Efficiency and accuracy of both, physical and surrogate, modeling techniques will be compared using a Si process technology.

Bottom-up synthesis approaches based on the hierarchical composition of performance models have been proposed as a promising alternative to conventional top-down hierarchical synthesis approaches. This paper discusses problems related to the context-dependence of performance models and proposes possible solutions. Techniques for the composition of multi-dimensional performance models so that the efficiency of the design space exploration is maximized are also discussed. An active filter is used to demonstrate the accuracy and efficiency of the techniques discussed here.

The design of complex analog circuits by using flat optimization-based approaches is inefficient, even impossible, due to the high number of design variables and the growth of the cost of performance evaluation with the circuit size. Over the past two decades, top-down hierarchical design approaches have been developed and applied. They are based on hierarchical circuit decomposition and specification transmission from top-level to lower level blocks. However, such specification transmission is usually performed with little knowledge on the feasibility of the specifications, leading, therefore, to costly redesign iterations. Even if the specification transmission is successful, there is no guarantee that it is optimal in terms of e.g., power consumption or area occupation. To palliate this problem, two novel model-based hierarchical synthesis methods are proposed in this paper: ModelBased Hierarchical Optimization (MBHO) and Improved ModelBased Hierarchical Optimization (IMBHO). They are based on the concurrent design at higher and lower hierarchical levels and appropriate communication between the different processes. Experimental results on a filter example comparing the new approaches and the conventional top-down design approach are provided.

Emerging hierarchical design methodologies based on the use of Pareto-optimal fronts (PoFs) are promising candidates to reduce the bottleneck in the design of analog circuits. However, little work has been reported about how to transmit the information provided by the PoFs of low hierarchical level blocks through the hierarchy to compose the performance models of higher-level blocks. This composition actually poses several problems such as the dependence of the PoF performances on the surrounding circuitry and the complexity of dealing with multi-dimensional PoFs in order to explore more efficiently the design space. To deal with these problems, this paper proposes new mechanisms to represent and select candidate solutions from multi-dimensional PoFs that are transformed to the changing operating conditions enforced by the surrounding circuitry. These mechanisms are demonstrated with the generation of the performance model of an active filter by composing previously generated PoFs of operational amplifiers.

In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.

A methodology to optimize the area of a fixed non-slicing floorplan is presented in this paper. Areas of transistors, capacitors and resistors are formulated as convex functions and area is minimized by solving a sequence of convex problems. The methodology is practical even with many components and variants. Moreover symmetry constraints are satisfied during optimization.

In engineering design and manufacturing optimization, the trade-off between a quality performance metric and the probability of satisfying all performance specifications (yield) of a product naturally leads to a chance-constrained bi-objective stochastic optimization problem (CBSOP). A new method, called MOOLP (multi-objective uncertain optimization with ordinal optimization (OO)), Latin supercube sampling and parallel computation), is proposed in this paper for dealing with the CBSOP. This proposed method consists of a constraint satisfaction phase and an objective optimization phase. In its constraint satisfaction phase, by using the OO technique, an adequate number of samples are allocated to promising solutions, and the number of unnecessary MC simulations for noncritical solutions can be reduced. This can achieve more than five times speed enhancement compared to the application of using an equal number of samples for each candidate solution. In its MOEA/D-based objective optimization phase, by using LSS, more than five times speed enhancement can be achieved with the same estimation accuracy compared to primitive MC simulation. Parallel computation is also used for speedup. A real-world problem of the bi-objective variation-aware sizing for an analog integrated circuit is used in this paper as a practical application. The experiments clearly demonstrate the advantages of MOOLP.

Surrogate model assisted evolutionary algorithms are receiving much attention for the solution of optimization problems with computationally expensive function evaluations. For small scale problems, the use of a Gaussian Process surrogate model and prescreening methods has proven to be effective. However, each commonly used prescreening method is only suitable for some types of problems, and the proper prescreening method for an unknown problem cannot be stated beforehand. In this paper, the four existing prescreening methods are analyzed and a new method, called self-adaptive lower confidence bound (ALCB), is proposed. The extent of rewarding the prediction uncertainty is adjusted on line based on the density of samples in a local area and the function properties. The exploration and exploitation ability of prescreening can thus be better balanced. Experimental results on benchmark problems show that ALCB has two main advantages: (1) it is more general for different problem landscapes than any of the four existing prescreening methods; (2) it typically can achieve the best result among all available prescreening methods.

In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires many yield estimations, practical. In this paper, techniques inspired by computational intelligence are used to speed up yield optimization without sacrificing accuracy. A new sampling-based yield optimization approach, which determines the device sizes to optimize yield, is presented, called the ordinal optimization (OO)-based random-scale differential evolution (ORDE) algorithm. By proposing a two-stage estimation flow and introducing the OO technique in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed evolutionary algorithm that uses differential evolution for global search and a random-scale mutation operator for fine tunings, the convergence speed of the yield optimization can be enhanced significantly. With the same accuracy, the resulting ORDE algorithm can achieve approximately a tenfold improvement in computational effort compared to an improved MC-based yield optimization algorithm integrating the infeasible sampling and Latin-hypercube sampling techniques. Furthermore, ORDE is extended from plain yield optimization to process-variation-aware single-objective circuit sizing.

In this paper, the application of multi-objective evolutionary algorithms to the evaluation of performance trade-offs of planar inductors, an almost ubiquitous device in radio-frequency microelectronics, is studied. The absence of appropriate stopping criteria in most evolutionary algorithms reveals to be critical in this application. A new stopping criterion based on monitoring a set of performance metrics that account for convergence and diversity is proposed and demonstrated with practical radio-frequency circuit design problems.

Recently, a multiobjective evolutionary algorithm based on decomposition (MOEA/D) and its extended version by using differential evolution (DE) as the main search engine (MOEA/D-DE) were proposed, which outperform several widely used multiobjective evolutionary algorithms. MOEA/D decomposes a multiobjective problem into a number of scalar optimization sub-problems with a neighborhood structure and optimizes them simultaneously to approximate the Pareto-optimal set. In this paper, two mechanisms are investigated to enhance the performance of MOEA/D-DE. Firstly, a new replacement mechanism is proposed to call for a balance between the diversity of the population and the employment of good information from neighbors. Secondly, the scaling factor in DE is randomized to enhance the search ability. Comparisons are carried out with MOEA/D-DE on ten benchmark problems, showing that the proposed method exhibits significant improvements. Finally, the enhanced MOEA/D-DE is applied to a real world problem, the sizing of a folded-cascode amplifier with four performance objectives.

Monte-Carlo (MC) simulation is still the most commonly used technique for yield estimation of analog integrated circuits, because of its generality and accuracy. However, although some speed acceleration methods for MC simulation have been proposed, their efficiency is not high enough for MC-based yield optimization (determines optimal device sizes and optimizes yield at the same time), which requires repeated yield calculations. In this paper, a new sampling-based yield optimization approach is presented, called the Memetic Ordinal Optimization (OO)-based Hybrid Evolutionary Constrained Optimization (MOHECO) algorithm, which significantly enhances the efficiency for yield optimization while maintaining the high accuracy and generality of MC simulation. By proposing a two-stage estimation flow and introducing the OO technology in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed memetic search operators, the convergence speed of the algorithm can considerably be enhanced. With the same accuracy, the resulting MOHECO algorithm can achieve yield optimization by approximately 7 times less computational effort compared to a state-of-the-art MC-based algorithm integrating the acceptance sampling (AS) plus the Latin-hypercube sampling (LHS) techniques. Experiments and comparisons in 0.35 ¿m and 90 nm CMOS technologies show that MOHECO presents important advantages in terms of accuracy and efficiency.

In this paper, a fuzzy selection-based differential evolution algorithm (FSBDE) for analog cell sizing is investigated. By combining the selection-based constraint handling method and fuzzy membership functions, a new selection methodology for handling fuzzy constraints is proposed and is integrated with the differential evolution (DE) algorithm to construct FSBDE. FSBDE specializes in solving analog sizing problems capturing imprecise human intentions, both avoiding the inflexibility of crisp constraint sizing methods and the excessive relaxation of available fuzzy sizing approaches. The high optimization ability of the DE algorithm is also inherited in this approach. Comparisons are carried out with the crisp selection-based differential evolution algorithm (SBDE) and DE in conjunction with available fuzzy optimization methods, showing that the proposed FSBDE algorithm presents important advantages in terms of fuzzy constraint handling ability and optimization quality.

This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local search ability by properly combining operators from different standard evolutionary algorithms. By integrating operators from the differential evolution algorithm, from the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes in handling analog circuit design problems with numerous and tight design constraints. The method has been tested through the sizing of several analog circuits. The results show that design specifications are met and objective functions are highly optimized. Comparisons with available methods like genetic algorithm and differential evolution in conjunction with static penalty functions, as well as with intelligent selection-based differential evolution, are also carried out, showing that the proposed algorithm has important advantages in terms of constraint handling ability and optimization quality.

In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascadeΣΔmodulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.

This paper presents design considerations for cascade sigma-delta modulators (SAMs) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1L-2expandible SigmaDeltaM is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach

This paper presents the design of a continuous-time multibit cascade 2-2-1 DeltaSigma modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 0.13mum CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth

This paper presents the design of a continuous-time multibit cascade 2-2-1 ΣΔmodulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.

This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time (DT) and continuous-time (CT) circuit techniques.

This paper introduces a very efficient methodology for the retargetability of embedded mixed-signal blocks for SoCs. The key parts of this methodology are: parameterised layout templates at different hierarchical levels, accurate behavioral modeling of mixed-signal blocks and appropriate mechanisms to tuning sized circuits to new sets of specs.

This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the analysis process. Consequently, the circuit sizes that can be analyzed increase dramatically, without suffering from the combinatorial explosion of expression complexity. Moreover the interpretability and usability in practical applications is enabled by providing analytical models that keep complexity at a minimum with the prescribed accuracy.

Summary form only given. This paper presents a user-friendly tool which allows automated sizing of IC cells. It comprises an open optimization-based sizing program, a database which allows knowledge re-use and also easy addition of new knowledge, and a powerful graphical user interface.

Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.

The use of simplification before generation techniques to enable the approximate symbolic analysis of large analog circuits is discussed. This paper introduces an error control mechanism to drive the circuit reduction, which overcomes the accuracy problems of previous approaches. The features and efficiency of the new methodology are demonstrated through several practical examples.

A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from statistical deviations in the technological parameters of MOS transistors. Performance is demonstrated via the analysis of a Miller OTA in two different configurations and a linearized CMOS transconductor. The CPU time is reduced by a factor of 25 to 90 with respect to conventional Monte Carlo simulation, while maintaining similar accuracy in the computations.

The aim of this forum session is to stimulate a discussion and an exchange of ideas on the advantages and disadvantages of symbolic analysis. The focus of the discussion is on the feasibility of the symbolic approaches in circuit design and the role they can and/or cannot play in the circuit CAD world.>

A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed. The CPU time and memory requirements are reduced drastically with regard to previous approaches, as only those terms are calculated which will remain in the final expression. As a consequence, the maximum circuit size amenable to symbolic analysis has largely increased. The simplification procedure explicitly takes into account variation ranges of the symbolic parameters to avoid inaccuracies of conventional approaches which use a single value. The new approach is also able to take into account mismatches between the symbolic parameters.>

Simplification techniques for nested symbolic expressions obtained by hierarchical analysis procedures are presented. An algorithm where potential ranges of variation in the symbolic parameter values are considered to perform simplifications is presented. In this approach, the relative significance of each expression at the different nested levels is evaluated prior to performing simplification. Thus, only those terms with little influence on the top expression are eliminated.>