The need for high throughput low latency FFT implementation in communication systems has led to the evolution of different architectures with multiple parallel inputs and outputs. This paper presents a novel generic hybrid architecture for parallel pipelined radix-2kFFT using FF (Feed Forward) architecture which is also known as MDC (Multi-path Delay Commutator). The proposed architecture offers a new FFT data buffering algorithm for a parallel pipelined normal order inputs FFT using MDC. Our architecture offers a great reduction in latency up to 25% when compared to state of the art parallel pipelined FFT architectures. This latency reduction is achieved as the total number of buffers needed for an N-point FFT doesn't exceed 1.5N and approaches N in some cases. In addition to that, the proposed architecture doesn't depend on the implementation of butterfly (BF) or rotation operation. Although the presented work is for radix-2kFFT, it can be generalized to radix-r.

In order to achieve higher transmission rates and system capacities, fifth generation (5G) systems as well as 802.11 ad/ay systems consider higher frequency bands (24GHz-70GHz), the so-called millimeter wave frequencies. These systems rely heavily on Orthogonal Frequency Division Multiplexing (OFDM) approach in order to realize the transmitted signal. The Fast Fourier Transform (FFT) and inverse FFT (IFFT) blocks are vital signal processing components in synthesizing the OFDM signal. Towards the objective of designing a low-complexity, small area, and low-power consumption FFT blocks, this paper proposes an extension of the algorithmic level approach, known as COordinate Rotation DIgital Computer (CORDIC)-Friendly FFT in [1], to a more practical higher order FFTs and mixed-radix FFTs. Moreover, it introduces the first quantization error analysis of a generalized mixed-radix FFT. The error analysis is used to find the optimal modified twiddle factors that reduce the FFT hardware complexity. Additionally, this paper shows that any type of CORDIC considered in the proposed framework outperforms the conventional FFT in terms of Signal-to-Quantization-Noise Ratio (SQNR), for a given silicon area budget. The proposed framework offers up to 50 dB SQNR gain compared to the conventional FFT for different FFT sizes when CORDIC rotators are employed. If Single-path Delay Feedback (SDF) pipeline architecture is used, the achieved SQNR gain is obtained at no additional hardware cost.

In this work we present a new 64-bit floating point Fused Multiply Add (FMA) unit that can perform both binary and decimal addition, multiplication, and fused-multiply-add operations. The presented FMA has 6 percent less delay than the fastest stand-alone decimal unit and 23 percent less area than both binary and decimal units together. These results were achieved by the use of: 1) column by column reduction to reduce the partial products in the multiplier tree, 2) a new leading zeros detector that produces its output in base-3 to simplify the normalization shifting in the binary datapath, 3) the use of a redundant adder to perform the final addition, 4) using a new rounding-while-redundant technique to hide the rounding delay and remove it from the critical path, and 5) using a new simple conversion technique from redundant to binary/decimal.

Language standards such as C99 and C11, as well as the IEEE Standard for Floating-Point Arithmetic 754 (IEEE Std 754-2008) specify the expected behavior of binary and decimal floating-point arithmetic in computer-programming environments and the handling of special values and exception conditions. Many researchers focus on verifying the compliance of implementations for binary and decimal floating-point operations with these standards. In this article, we are concerned with the special values of the operands of the power function Z = X Y . We study how the standards define the correct results for this operation, propose a mathematically justified definition for the correct results of the power function on the occurrence of these special values as its operands, test how different software implementations for the power function deal with these special values, and classify the behavior of different programming languages from the viewpoint of how much they conform to the standards and our proposed mathematical definition. We present inconsistencies between the implementations and the standards, and discuss incompatibilities between different versions of the same software.

Decimal floating-point is a relatively recent addition to the IEEE standard (IEEE Std 754-2008). There exist few verification techniques that can check whether software libraries or hardware designs are in compliance with the standard. Our work presents a verification method to verify implementations of the decimal floating-point square root operation. We present an effective simulation based verification technique using test cases that verify the corner cases of the operation. The test cases are generated by solving constraints describing these corner cases with a dedicated constraint solver. The generated test cases proved their usefulness by finding severe bugs in two well-tested designs.

Intensive scaling for VLSI circuits is a key factor for gaining outstanding performance. However, this scaling has huge negative impact on the circuit reliability, as it increases the undesired effect of aging degradation on ultradeep submicrometer technologies. Nowadays, Bias Temperature Instability (BTI) aging process has a major negative impact on VLSI circuits reliability. This paper presents a comprehensive framework that assists in designing the fortified VLSI circuits against BTI aging degradation. The framework contains: 1) the novel circuit level techniques that eliminate the effect of BTI (these techniques successfully decrease the power dissipation by 36% and enhance the reliability of VLSI circuits); 2) the evaluation of the reliability of all circuit level techniques used to eliminate BTI aging degradation for 16 nm CMOS technology; and 3) the comparison between the efficiency of all circuit level techniques in terms of power consumption and area.

In this paper, two BCH soft decoders are proposed suitable for high rate codes with medium to large word length. The proposed decoders provide a programmable performance gain, with a reduced critical path allowing for an increase upto m/2 times the operating frequency of algebraic decoders, where m is the Galois field size. Our proposed decoders operate only on the least reliable bits, which leads to a reduction in the decoder complexity by removing the Chien search procedure.

Decimal floating-point fused-multiply-add (FMA) software or hardware designs require a verification process to prove that the design is in compliance with the IEEE Standard for Floating-Point Arithmetic (IEEE Std 754-2008). Our work represents the first verification technique to verify the decimal FMA designs using simulation based coverage models. The paper describes in details the coverage models needed in the verification of the decimal FMA, the FMA engine used to solve the coverage models, and the results of using that technique in the verification of SilMinds FMA hardware design, DecNumber FMA software design, and Intel-Decimal Floating point Library FMA software design. The Technique has proven its efficiency in discovering bugs in FMA software and hardware designs.

This paper presents an efficient architecture to handle memory conflicts of a unified turbo decoder which supports multiple standards like HSPA+, 3GPP-LTE, WiMAX, 3GPP2-CDMA2000 and CCSDS. A unified radix-4 turbo decoder is used as the reconflgurable unit which provides double throughput for some standards. A complete memory conflict analysis for different interleaver patterns has been performed and shows the effect of using radix-4 decoding on the memory conflicts for different standards. Such a conflict adds latency and reduces the throughput significantly. A simple controller is designed to manage the conflicts on the fly. The proposed design has a maximum throughput of 283.104 Mbps.

In this paper, an Application Specific Instruction-set Processor (ASIP) architecture to perform all OFDM synchronization tasks is proposed. While applicable to many OFDM systems, the proposed architecture is tested on Long Term Evolution (LTE Rel. 8) and WiMAX 802.16e systems. The synchronization tasks include, but not limited to symbol timing, fine carrier frequency offset (CFO) estimation, coarse CFO estimation, cell search, residual CFO estimation and sampling clock frequency offset estimation. The engine is scalable and runs at 120 MHz with a total gate count of 118k and control overhead less than 10% of total processing cycles. The results of software simulations as well as the results of verilog synthesis are presented.

Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the authors knowledge, this is the first work to discuss energy savings in DFP and the first to present a hardware implementation of a fused multiply-add. Our Newton-Raphson based divider is over three times faster than the similar design previously reported.

Elementary and high-level functions can be computed in hardware using polynomial approximation techniques. There are many techniques in the literature to calculate the coefficients of such polynomials. Remez algorithm as presented by Veidinger (1960) provides the optimal polynomial in the Chebyshev sense that is minimizing the maximum error (minimax approximation). This paper presents an algorithm for truncating the coefficients of the minimax polynomials obtained from Remez algorithm using an algorithmic method. A gain of 3 and 4 bits of accuracy over the direct rounding is reported. Muller addressed the same problem but his algorithm is applicable for the second order polynomials only. This paper presents an algorithm that is applicable for any order

We use a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder using the proposed format is presented and the specific challenges of the design are explained. A brief description of a multiplier and divider using the proposed format is also presented. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard. Transistor simulation of the adder and multiplier confirm the performance advantage predicted by the analytical model.