High-linearity current-steering DACs are critical components in wireless and wireline communication systems, but are notoriously time-consuming to design. Nonlinearity from component mismatches and clock skew can be mitigated with DEM and calibration, but the remaining sources of nonlinearity must be managed by painstaking analog design iteration. Typically, exceedingly long circuit simulations, e.g., each on the order of many days, are required to guide the iteration process, which makes for long design cycles. This paper presents an enhanced analysis of DAC error from component mismatches, clock skew, and inter-symbol interference, and applies the results to enable a new circuit-level simulation technique to quantify nonlinearity that is significantly faster than conventional techniques without sacrificing accuracy. It demonstrates via analysis and simulation examples that the technique enables over an order of magnitude speed increase of circuit-level simulations of high-linearity, high-speed, current-steering DACs.

Increasing a PLL’s reference frequency offers significant performance advantages, but doing so by increasing the PLL’s crystal oscillator frequency is not a viable option in many applications. Instead, a frequency doubler can be used to derive a reference signal with twice the frequency of the crystal oscillator, but conventional PLLs are highly sensitive to the crystal oscillator’s duty cycle error in such cases. Prior solutions to this problem involve calibration techniques which impose convergence speed versus accuracy tradeoffs. In contrast, this paper proposes a system modification which makes a PLL immune to such duty cycle errors without the need for calibration. The technique is presented and analyzed in the context of a delta-sigma frequency-to-digital converter ($\Delta \Sigma $-FDC) based PLL. Analysis and behavioral simulations with nonideal circuit parameters show that the worst-case convergence time is at least 10 times faster than that of the prior techniques. Additionally, the proposed$\Delta \Sigma $-FDC includes other modifications which improve its performance relative to comparable prior$\Delta \Sigma $-FDCs.

Inter-symbol interference (ISI) often limits the performance of high-speed continuous-time digital-to-analog converters (DACs) such as Nyquist-rate current-steering DACs. The most effective previously-published means of mitigating ISI is return-to-zero (RZ) pulse shaping. Unfortunately, such RZ DACs are significantly more sensitive to clock jitter than their non-return-to-zero (NRZ) counterparts, particularly at high clock rates, and they typically consume more than twice the power of comparable NRZ DACs. This paper proposes, demonstrates via simulation, and rigorously analyzes a calibration technique which circumvents the need for RZ pulse shaping by adaptively measuring and cancelling ISI over the DAC’s first Nyquist band. It can be operated in both foreground and background calibration modes, and is compatible and can share circuitry with a recently-published calibration technique that similarly cancels error from component mismatches and clock skew.

Digital-to-time converter (DTC) based quantization noise cancellation (QNC) has recently been shown to enable excellent fractional-$N$PLL performance, but it requires a highly-linear DTC. Known DTC linearization strategies include analog-domain techniques which involve performance tradeoffs and digital predistortion techniques which converge slowly relative to typical required PLL settling times. Alternatively, a DTC implemented as a cascade of 1-bit DTC stages can be made highly linear without special techniques, but such DTCs typically introduce excessive error from component mismatches which has so far hindered their use in low-jitter PLLs. This paper presents a background calibration technique that addresses this issue by adaptively canceling error from DTC component mismatches. The technique is entirely digital, is compatible with a large class of digital fractional-$N$PLLs, and has at least an order of magnitude lower convergence time than the above-mentioned predistortion techniques. The paper presents a rigorous theoretical analysis closely supported by simulation results which quantifies the calibration technique’s convergence time and noise performance.

This paper describes all-digital enhancements for digital fractional-N phase-locked loops (PLLs) based on delta-sigma (ΔΣ) frequency-to-digital converters (FDCs). The enhancements include an improved dual-mode ring oscillator (DMRO)-based ΔΣ FDC architecture and a digital background calibration technique that compensates for the ΔΣ FDC's forward path gain error. The improved ΔΣ FDC has significantly relaxed timing constraints and a 3× smaller phase-frequency detector output pulse-width span relative to the prior art, which make it simpler to implement and amenable to higher-frequency reference signals. The calibration technique compensates for non-ideal DMRO frequencies in the digital domain. It eliminates the need to tune the DMRO instantaneous frequencies as a function of the PLL output frequency, thereby simplifying the DMRO implementation, and it also improves the phase noise performance of PLLs with high loop bandwidths.

Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits.

Mismatch-shaping DAC have become widely used in high-performance delta-sigma data converters in recent years. Nevertheless, no theoretical results have been published to date that quantify their performance, so designers have been forced to rely on simulation-based analyses. This paper presents the first theoretical performance analysis of a mismatch-shaping DAC. Specifically, the PSD of the mismatch noise introduced by a first-order tree-structured DAC within a second-order ADC delta-sigma modulator with a midscale constant input signal is derived. This particular mismatch-shaping DAC and delta-sigma modulator configuration was chosen for analysis because it has been demonstrated experimentally to achieve state-of-the-art ADC performance. The choice of a constant midscale input was made because simulation and experimental results suggest that it yields the worst-case performance.

Digital phase-locked loops (DPLLs) that operate in an analogous fashion to delta-sigma (/spl Delta//spl Sigma/) modulator A/D converters have been recently proposed. Although they offer certain advantages over conventional DPLLs, their direct implementation requires components that are difficult to realize without high-precision analog circuitry. This paper presents an alternate mechanization approach that gives rise to systems that have the same theoretical performance as those presented previously but consist of easily implemented components such as analog integrators, digital flip-flops, and digital counters.

This paper presents an A/D converter architecture in which four 4/sup th/ order /spl Delta//spl Sigma/ modulator channels are operated in parallel at a time-oversampling ratio of 10 to obtain an ideal signal-to-quantization error ratio corresponding to 18-bits. The architecture has the property that any x-bit decrease in individual /spl Delta//spl Sigma/ modulator conversion performance due to non-ideal circuit behavior causes an x+1-bit decrease in the overall A/D conversion performance. The additional error caused by gain and offset mismatches among the four channels is either tolerable or removable using a simple digital compensation scheme. Thus, much of the robustness of /spl Delta//spl Sigma/ modulators is preserved.

Techniques have recently been proposed for simultaneously performing angle-demodulation and A/D conversion that offer the potential of reduced circuit complexity over conventional approaches. The techniques give rise to systems that operate on the instantaneous frequency of an angle modulated input signal in the same manner that /spl Sigma//spl Delta/ modulators operate on instantaneous amplitude. This paper presents various new structures that are analogous to higher-order /spl Delta//spl Sigma/ modulators in terms of their quantization noise shaping capabilities. The tradeoffs associated with the higher-order systems are discussed, and simulations are presented.>

The trend toward digital signal processing in communication systems has resulted in a large demand for fast accurate analog-to-digital (A/D) converters, and advances in VLSI technology have made /spl Delta//spl Sigma/ modulator-based A/D converters attractive solutions. However, rigorous theoretical analyses have only been performed for the simplest /spl Delta//spl Sigma/ modulator architectures. Existing analyses of more complicated /spl Delta//spl Sigma/ modulators usually rely on approximations and computer simulations. In the paper, a rigorous analysis of the granular quantization noise in a general class of /spl Delta//spl Sigma/ modulators is developed. Under the assumption that some input-referred circuit noise or dither is present, the second-order asymptotic statistics of the granular quantization noise sequences are determined and ergodic properties are derived.>

A unified approach to analyzing the granular quantization error of the first-order Delta Sigma modulator is presented. The approach handles many of the previously analyzed input sequences in addition to a large class of new input sequences. By averaging over the arbitrarily small amount of circuit noise assumed to be present at the analog input to the Delta Sigma modulator, a simple expression for the autocorrelation of the quantization error is derived. Each term in the expression is formally equal to the quantization error of a nonoverloaded uniform quantizer operating upon a finite partial sum of consecutive input sequence samples. Hence, existing results concerning uniform quantizers are directly applicable in evaluating the autocorrelation expression for specific input sequences. The theory is also applicable to deterministic input sequences, and has been applied to obtain a new closed-form result for sinusoidal input sequences. Ergodic results which assert that, under mild conditions, the autocorrelation equals the time-average autocorrelation in probability are presented.>