Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the network, using JAVA technology. The paper demonstrates that FPGAs are a realistic implementation platform for thin server or client applications. FPGAs can offer the same end-user experience as software based systems, combined with more computational power and lower cost.

Summary form only givem, as follows. In the last decade and a half, Field Programmable Gate Arrays (FPGAs) have grown from simple devices with a few hundred programmable logic gates to densities beyond one million gates. This growth in density has led to an ever-expanding area of application for these devices. From their early use as simple interface or "glue" logic, FPGAs have moved on to become popular platforms for implementing system bus interfaces, including industry standards such as PCI. As device density has surpassed one million gates, FPGA co-processing in data-intensive applications such as Digital Signal Processing (DSP) and networking has become commonplace. The recent announcement of the Virtex II FPGA+CPU device from Xilinx, as well as similar announcements from other vendors, indicate that the trend toward single chip FPGA+CPU processing will continue. And with ten million gate devices under development, it is expected that more system functionality, including more general purpose processing, will continue to migrate into the FPGA. While much of this type of coprocessing can also be accomplished with fixed Application Specific Integrated Circuit (ASIC) hardware, the ability to reprogram FPGA devices, even in system, opens up new opportunities for system design. Reconfigurable logic provides new methods for increasing performance, decreasing power consumption and increasing system functionality. Along with these new benefits come challenges, particularly in the area of software design tools. Tools such as Xilinx's JBits point the way toward providing a single unified environment for programming CPUs, configuring and reconfiguring hardware resources and providing integrated debug support for the single chip reconfigurable systems of the future.

The ability to tolerate defects in semiconductor devices has the potential for both increasing yields of devices being manufactured and making it economically feasible to manufacture even larger devices. While FPGA devices appear to be well suited to providing defect tolerance, practical application of existing research and techniques has been somewhat elusive. One barrier to acceptance is that existing defect tolerance techniques for FPGAs have tended to rely on either modifications to device architectures or modifications to design tools. We describe a software-based technique for providing defect tolerance which requires neither changes to device hardware or software tools. This approach uses the Xilinx JBits$^{(tm)}$ toolkit and operates at the core library level. Addressing defect tolerance locally using core library elements rather than taking a global approach helps provide direct support for run-time reconfiguration. Circuits may be configured and reconfigured rapidly in the presence of these defects. This rapid configuration also provides a path for practical use in more traditional manufacturing environments.

As FPGA devices have increased in density, the demand for pre-designed logic modules or cores has increased correspondingly. These cores permit reuse of portions of existing designs, reducing the overall design effort. Currently, nearly all cores are specified in some static netlist-oriented format. Such specifications are not well suited for use in a run-time reconfigurable or runtime customizable environment. This paper describes JBitsDiff, a tool constructed using Xilinx's JBits/sup TM/ software, which extracts circuit information directly from configuration bitstreams and produces pre-routed and pre-placed cores suitable for use at run time. Further work to produce parameterizable and reconfigurable cores using JBitsDiff, and some of the pitfalls encountered are also discussed.

No abstract available.