This work presents a modification of traditional Oscillation-Based Test schemes for sampled-data systems. This new test scheme is based on doubling the sampling frequency when the oscillation changes its sign. This way, the DC level of the output oscillation signal becomes a simple signature sensitive to the settling errors in the device under test and to its oscillation features. The proposed technique is illustrated on a switched-capacitor second-order lowpass filter. This case study is used to show the sensitivity of the proposed signature to the linearity of the DUT. Electrical simulation results are provided to validate the proposal.

This work demonstrates that multi-VDDconditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90 nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.

This paper presents practical solutions for two of the main topics arising when applying oscillation-based-test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

This paper presents a BIST scheme for the structural testing of pipelined ADCs. The operational principle relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a set of analog DC values. These values have been determined as the appropriate and simple stimuli giving a single output signature. A new output signature is proposed allowing a low-cost digital domain test evaluation. The new technique is intended to be used in pipelined converters of an arbitrary number of conversion stages and provided with a digital correction mechanism.

This paper presents an operational method for converting into digital the analog waveforms resulting when oscillation-based test (OBT) is applied to a mixed signal integrated circuit. Although our aim is OBT this technique can be used in structural testing in general. A complex mixed-signal macrocell is used as an example to demonstrate the pros and cons of the technique.

This paper proposes a methodology for designing sampled-data mixed-signal circuits by using VHDL-based behavioural descriptions. The goal is using a VHDL description of both the analog and the digital part, to simulate and verify the entire mixed-signal system, as well as to facilitate the synthesis and fault simulation of the digital part. As an example of the proposed methodology, a digitally corrected/calibrated pipeline A/D converter (ADC) has been designed. Among other aspects of general interest, we show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. Results from simulations carried out using QuickHDL in MentorGraphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a silicon prototype.

This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.

Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column based algorithm to solve this optimization problem. The new algorithm targets economical implementation of face constraints unlike conventional algorithms which do not care about infeasible ones. Experimental results that demonstrate the superiority of the new method versus conventional tools and a preview algorithm specifically developed for the minimum length encoding problem are shown. A state assignment tool which uses the new algorithm is evaluated by implementing a standard benchmark of sequential circuits. It compares very favorably to well known tools like NOVA.

This paper deals with a case study applying oscillation-based testing to an industrial circuit. The aim of the presentation is to discuss a practical way of carrying out an effective implementation of the oscillation test technique as well as discussing guidelines for its application.

Traditionally, state assignment algorithms follow the two-step strategy of first constraint generation and secondly constraint-guided encoding. There are well known drawbacks in both currently used models for constraint generation. Approaches following the input model generate face constraints without taking into account the sharing of logic among next state lines. Approaches following the input-output model generate face constraints for a priori determined set of dominance/disjunctive relations among the codes of the states which may not hold in final encoding. To overcome these limitations, we propose a dynamic input model which implements both the above cited steps concurrently. The dynamic constraints are of the face type but they are generated during the encoding process and so take advantage of actual relations among partial codes. A general algorithm based on this model and which can target two-level as well as multiple-level implementations is described. Results obtained with the algorithm on the IWLS'93 machines are shown and they compare favorably with standard tools.

An approach to test optimization in switched-capacitor systems based on fault simulation at switch-level is presented in this paper. The advantage of fault simulation at this granularity level is that it facilitates test integration as early as possible in the design of these systems. Due to their mixed-signal nature, both catastrophic and parametric faults must indeed be considered for test optimization. Adequate switch-level fault models are presented. Test stimuli and test measures can be selected as a function of fault coverage. The impact of design parameters such as switch resistance on fault coverage is studied and design parts of poor testability are located.

This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.

This paper addresses the practical implementation of a Design-for-Testability (DfT) technique applicable to digitally-corrected pipelined Analog-to-Digital Converters (ADC). The objective of this Dft is to improve both the on-and off-line testability of these important mixed-signal ICs. Because of the self-correction capability, such a kind of converters has some inherent insensitivity to the effect of faults which represents a disadvantage for testing and diagnosis. We will show that potentially malfunctioning units can be concurrently identified with low extra circuitry. In addition, this structure-based DfT scheme can also be useful to reduce the time in production-level testing. A CMOS switched-capacitor 10-b ADC is used as demonstrator of the proposed technique.

This communication presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing in a Smart-Substrate MCM. Three different self-timed asynchronous scan cells are proposed (Sense, Drive and Drive and Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode.

A tool for the switch-level fault simulation and test evaluationof switched-capacitor systems is presented. Time or frequency-domainfault simulations with SWITCAP and time-domain faultsimulations with HSPICE can be performed. Adequate fault modelsare presented for both simulators. The tool has proven to bevery useful in the early evaluation of test strategies, providing similarresults to those obtained at the transistor-level.

The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

Pipeline or sub-ranging architectures enable the implementation of high-speed, low-power and high-resolution Analog-to-Digital Converters (ADCs). It is usual in these architectures to include digital correction to reduce the sensitivity to certain component nonlinearities, such as comparator offsets and settling errors. However, digital correction makes difficult the detection of defective operation because some errors could not be revealed in the output code under nominal test conditions but could appear when operation conditions change. This paper presents a Design-for-Testability (DFT) technique for concurrent error detection in digitally-corrected pipelined ADCs. The approach is based on hardware redundancy, requiring an additional sub-DAC, a window comparator and some control logic. The effectiveness of the technique has been evaluated by means of fault simulations in a switched-capacitor 10-bit ADC application example.

This paper discusses architectural and circuit-level aspects related to hardware realizations of fuzzy controllers. A brief overview on fuzzy inference methods is given focusing on chip implementation. The singleton or zero-order Sugeno's method is chosen since it offers a good tradeoff between hardware simplicity and control efficiency. The CMOS microcontroller described herein processes information in the current-domain, but input-output signals are represented as voltage to ease communications with conventional control circuitry. Programming functionalities are added by combining analog and digital techniques, giving rise to a versatile microcontroller, capable of solving different control problems. After identifying the basic component blocks, the circuits used for their implementation are discussed and compared with other alternatives. This study is illustrated with the experimental results of prototypes integrated in different CMOS technologies.

This paper focuses on the implementation of the 'sw-op amp' concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell.

No abstract available.

This paper presents a method to characterize Nyquist rate A/D converters based on the use of a first order statistical behavioral model. The proposed model is derived from a very basic statistical interpretation of the conversion operation which contemplates noise and statistical process variations effects on traditional converter parameters. Both DC and dynamic converter parameters can be easily measured. The applicability of the proposed method is illustrated with two different examples. The first serves to show the possibility of deriving the statistical behavioral model from real measured data, and to prove the correctness of the model by comparing results to those obtained with traditional deterministic models. The second example illustrates the incorporation of the model in the mixed-signal simulator ELDO. The obtained results show that despite the model's simplicity, it is very efficient for quick and complete simulation of data converters.

A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from statistical deviations in the technological parameters of MOS transistors. Performance is demonstrated via the analysis of a Miller OTA in two different configurations and a linearized CMOS transconductor. The CPU time is reduced by a factor of 25 to 90 with respect to conventional Monte Carlo simulation, while maintaining similar accuracy in the computations.

In this paper we study stability problems associated with the previously developed design for test (DFT) methodology applied to ladder filters. A solution based on simple modification of the basic DFT strategy is proposed which allows on-line testing of ladder filters. A filter example demonstrates the feasibility of the solution.

The purpose of this paper is to present a novel modular N-user asynchronous arbiter circuit which is insensitive to metastable operation (i.e., the new arbiter cannot fail because of metastability), operating asynchronously and incorporating a modular architecture. A 1.5 /spl mu/m CMOS prototype arbiter has been designed and tested. Laboratory tests demonstrate the arbiter operates correctly.

This communication reports a new modeling of opamp-induced harmonic distortion in SC /spl Sigma//spl Delta/ modulators, which is aimed at the optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer of charge in a SC integrator and use power expansion and nonlinear fitting to obtain analytical models to represent harmonic distortion as function of the opamp finite gain-bandwidth (GB), slew-rate (SR) and nonlinear DC gain. Calculated models apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. We show that results provided by the new analytical models fit well to that obtained by simulation in time domain and have accuracy levels much larger than that provided by previously reported modeling approaches.>

This paper presents an optimization algorithm which simultaneously deals with the problems of placement and global routing in an analog macrocell layout style. The optimization process is based on a simulated annealing algorithm. We evaluate the physical placement of the cells and estimate the global routing for each intermediate solution generated. The basic idea, that together with an appropriate heuristic make the algorithm extremely efficient, consist of maintaining the same basic representative structure (slicing structures) for both problems. This method enables us to impose symmetry conditions and to penalize the existence of sensitive and noisy nets in the same channel.>

Taking advantage of the structural properties of some universal biquads, a low-cost strategy for off-line testing analog filters has been developed. This new strategy consists in provoking pole-zero cancellation during the test mode operation, without eliminating information about parameters which determine the normal circuit operation. Although area overhead could seem high, it can be very small in many applications.>

The influence of the main source of errors in Switched-Current (SI) filters over the performance of Wave Analog Filters (WAE) is evaluated. Models of mismatching and clock-feedthrough (CF) are deduced for basic building blocks, and applied to study the sensitivity of a third-order filter. Monte Carlo simulations performed using a behavior simulator prove that CF are dominant over mismatching effects.>

We describe an analog VLSI implementation of the ARTI algorithm (Carpenter, 1987). A prototype chip has been fabricated in a standard low cost 1.5~m double-metal single-poly CMOS process. It has a die area of lcm2 and is mounted in a 12O-pins PGA package. The chip realizes a modified version of the original ARTI architecture. Such modification has been shown to preserve all computational properties of the original algorithm (Serrano, 1994a), while being more appropriate for VLSI realizations. The chip implements an ARTI network with 100 F 1 nodes and 18 F2 nodes. It can therefore cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is possible by assembling an NxM array of chips without any extra interfacing circuitry, resulting in an F 1 layer with l00xN nodes, and an F2 layer with 18xM nodes. Pattern classification is performed in less than 1.8~s, which means an equivalent computing power of 2.2x109 connections and connection-updates per second. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, thus having a true asynchrounous digital behavior. Experimental chip test results are available, which have been obtained through test equipments for digital chips.

A new strategy for testing analog filters is presented, based on the reevaluation of the transfer function followed by simple processing of the output signals. Taking advantage of the structural properties of some universal biquads, this new strategy consists in provoking pole-zero cancellation during the test mode, without eliminating information about parameters which determine the normal circuit operation. Although area overhead could seem high, it can be very small in many applications.>

The transconductance-mode (T-mode) approach is extended to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. The demonstration vehicle used is a 5+5-neuron bidirectional associative memory (BAM) prototype fabricated in a standard 2-mum double-metal double-polysilicon CMOS process. Mismatches and nonidealities in learning neural hardware are not supposed to be critical if on-chip learning is available, because they will be implicitly compensated. However, mismatches in the learning circuits themselves cannot always be compensated. This mismatch is specially important if the learning circuits use transistors operating in weak inversion. The authors estimate the expected mismatch between learning circuits in the BAM network prototype and evaluate its effect on the learning performance, using theoretical computations and Monte Carlo HSPICE simulations. These theoretical predictions are verified using experimentally measured results on the test vehicle prototype.

Simplification techniques for nested symbolic expressions obtained by hierarchical analysis procedures are presented. An algorithm where potential ranges of variation in the symbolic parameter values are considered to perform simplifications is presented. In this approach, the relative significance of each expression at the different nested levels is evaluated prior to performing simplification. Thus, only those terms with little influence on the top expression are eliminated.>

Proposes a new solution to alleviate the area overhead when replication is used in switched-capacitor filters. This new approach, although based on the voter mechanism, only requires a programmable biquad and some control logic as extra components (instead of the full duplication of the system). To some extent, it can be considered a first intent to apply information redundancy for the concurrent test of analog circuits.>

A method for the state assignment of finite sequential machines is proposed. The algorithm gives solutions with a minimum number of state variables instead of with minimal-cardinality next-state functions. Comparisons between the results given by the proposed method and others previously reported have shown a clear superiority of the present algorithm in terms of silicon area, especially for big machines.>

A special-purpose analog computer made of switched-capacitor circuits is presented for analyzing chaos and bifurcation phenomena in nonlinear discrete dynamical systems modeled by discrete maps xn + 1= f(xn) Experimental results are given for four switched-capacitor circuits described by well-known discrete maps; namely, the logistic map, the piecewise-linear unimodal (one-hump) map, the Hénon map, and the Lozi map.

This correspondence proposes a generalization of the normal DON'T CARE condition and develops the input and next-state equations for a R-S type M-stable. An example is used to clarify the application of such a device to sequential machine inplementation.

A self-synchronization model is developed. It is based on a general clock function which depends only on the state variables. This function is associated with the flip-flop type to be used and is independent of the flow table. A modular implementation which uses integrated circuits is obtained. With this technique, the synthesis procedures for synchronous machines can be directly applicable to asynchronous circuits without taking care of the critical races and essential hazards.