The test-and-set object is a fundamental synchronization primitive for shared memory systems. This paper addresses the number of registers (supporting atomic reads and writes) required to implement a one-shot test-and-set object in the standard asynchronous shared memory model with n processes. The best lower bound is log n - 1 [12,21] for obstruction-free and deadlock-free implementations, and recently a deterministic obstruction-free implementation using O(√ n) registers was presented [11].

This article is concerned with the problem of implementing an unbounded timestamp object from multiwriter atomic registers, in an asynchronous distributed system of n processes with distinct identifiers where timestamps are taken from an arbitrary universe. Ellen et al. [2008] showed that √ n /2 − O (1) registers are required for any obstruction-free implementation of long-lived timestamp systems from atomic registers (meaning processes can repeatedly get timestamps). We improve this existing lower bound in two ways. First we establish a lower bound of n /6 − 1 registers for the obstruction-free long-lived timestamp problem. Previous such linear lower bounds were only known for constrained versions of the timestamp problem. This bound is asymptotically tight; Ellen et al. [2008] constructed a wait-free algorithm that uses n − 1 registers. Second we show that √2 n − log n − O (1) registers are required for any obstruction-free implementation of one-shot timestamp systems (meaning each process can get a timestamp at most once). We show that this bound is also asymptotically tight by providing a wait-free one-shot timestamp system that uses at most ⌈2√ n ⌉ registers, thus establishing a space complexity gap between one-shot and long-lived timestamp systems.

Herlihy and Wing [11] established that the set of possible outcomes of a shared memory distributed algorithm remains unchanged when atomic objects are replaced by their linearizable implementations. Since then, linearizability has been the correctness condition of choice for distributed algorithm designers. In 2011, however, Golab, Higham and Woelfel [9] showed that, if an algorithm employs randomization, then the probability distribution over the set of possible outcomes can differ between the atomic and implemented versions. They also proved that a stronger condition, called strong linearizability, is necessary and sufficient to guarantee the same probability distributions for these two cases when the randomized algorithm is under the control of an adaptive adversary. Therefore, we are motivated to construct strongly linearizable implementations of common distributed objects whenever possible. In this paper we prove

This paper is concerned with the problem of implementing an unbounded timestamp object from multi-writer atomic registers, in an asynchronous distributed system of n processors with distinct identifiers where timestamps are taken from an arbitrary universe. Ellen, Fatourou and Ruppert [7] showed that √n/2-O(1) registers are required for any obstruction-free implementation of long-lived timestamp systems from atomic registers (meaning processors can repeatedly get timestamps).

Linearizability is the gold standard among algorithm designers for deducing the correctness of a distributed algorithm using implemented shared objects from the correctness of the corresponding algorithm using atomic versions of the same objects. We show that linearizability does not suffice for this purpose when processes can exploit randomization, and we discuss the existence of alternative correctness conditions. This paper makes the following contributions: 1. Various examples demonstrate that using well-known linearizable implementations of objects (e.g., snapshots) in place of atomic objects can change the probability distribution of the outcomes that the adversary is able to generate. In some cases, an oblivious adversary can create a probability distribution of outcomes for an algorithm with implemented, linearizable objects, that not even a strong adversary can generate for the same algorithm with atomic objects. 2. A new correctness condition for shared object implementations, called strong inearizability, is defined. We prove that a strong adversary (i.e., one that sees the outcome of each coin flip immediately) gains no additional power when atomic objects are replaced by strongly linearizable implementations. In general, no strictly weaker correctness condition suffices to ensure this. We also show that strong linearizability is a local and composable property. 3. In contrast to the situation for the strong adversary, for a natural weaker adversary (one that cannot see a process' coin flip until its next operation on a shared object) we prove that there is no correspondingly general correctness condition. Specifically, any linearizable implementation of counters called terminating. from atomic registers and load-linked/store-conditional objects, that satisfies a natural locality property, necessarily gives the weak adversary more power than it has with atomic counters.

Shadow price and Vickrey price are two classic metrics that can be applied to measure the relative importance of links in a communication network. Each metric has been extensively investigated and enjoys important applications. We study the underlying connections between these two metrics with seemingly different definitions, under a general mathematical model of multipath multi-session multicast routing. We show that Vickrey prices provide upper-bounds for shadow prices in general, and the fine granularity version of Vickrey price, unit Vickrey price, equals exactly the maximum shadow price. We further design an efficient algorithm that computes all-link max/min shadow prices and unit Vickrey prices simultaneously, for unicast routing, reducing the complexity of a straightforward algorithm by an order of O(|E|).

No abstract available.

Write buffering is one of many successful mechanisms that improves the performance and scalability of multiprocessors. However, it leads to more complex memory system behavior, which cannot be described using intuitive consistency models, such as Sequential Consistency. It is crucial to provide programmers with a specification of the exact behavior of such complex memories. This article presents a uniform framework for describing systems at different levels of abstraction and proving their equivalence. The framework is used to derive and prove correct simple specifications in terms of program-level instructions of the sparc total store order and partial store order memories.The framework is also used to examine the sparc relaxed memory order. We show that it is not a memory consistency model that corresponds to any implementation on a multiprocessor that uses write-buffers, even though we suspect that the sparc version 9 specification of relaxed memory order was intended to capture a general write-buffer architecture. The same technique is used to show that Coherence does not correspond to a write-buffer architecture. A corollary, which follows from the relationship between Coherence and Alpha, is that any implementation of Alpha consistency using write-buffers cannot produce all possible Alpha computations. That is, there are some computations that satisfy the Alpha specification but cannot occur in the given write-buffer implementation.

A distributed system is commonly modelled by a graph where nodes represent processors and there is an edge between two processors if and only if they can communicate directly. In shared-registers versions of this general description, neighbouring processors communicate by reading or writing shared registers, where each read or write is one atomic step. Variants of shared register models occur in the literature. This paper defined two models of shared registers determined by selecting the register locations. In the atomic-state model each processor has a register; in the atomic-link model, each communication link has a register. We determine under what conditions and with what robustness and/or failure-tolerance guarantees it is possible to transform a solution under the atomic-state model into a solution under the atomic-link model. The fault-tolerant models considered in this paper are wait-freedom and self-stabilization. These questions are addressed by first establishing a framework for defining correct transformations, which may be useful for similar studies of the relationship between various models of distributed computation

Our general goal is to port programs from one multiprocessor architecture to another, while ensuring that each program's semantics remains unchanged. This paper addresses a subset of the problem by determining the relationships between memory consistency models of three Sparc architectures, (TSO, PSO and RMO) and that of the Itanium architecture. First we consider Itanium programs that are constrained to have only one load-type of instruction in {load, load _acquire}, and one store-type of instruction in {store, store_release}. We prove that in three out of four cases, the set of computations of any such program is exactly the set of computations of the "same" program (using only load and store) on one Sparc architecture. In the remaining case the set is nested between two natural sets of Sparc computations.Real Itanium programs, however, use a mixture of load, load acquire, store, store release and memory fence instructions, and real Sparc programs use a variety of barrier instruction as well as load and store instructions. We next show that any mixture of the loadtypes or the store-types (in the case of Itanium) or any barrier instructions (in the case of Sparc) completely destroys the clean and simple similarities between the sets of computations of these systems. Thus (even without considering the additional complications due to register and control dependencies) transforming these more general programs in either direction requires constraining the transformed program substantially more than the original program in order to ensure that no erroneous computations can arise.

Most weak memory consistency models are incapable of supporting a solution to mutual exclusion using only read and write operations to shared variables. Processor consistency-Goodman's version (PC-G) is an exception. Ahamad et al. showed that Peterson's mutual exclusion algorithm is correct for PC-G, but Lamport's bakery algorithm is not. This paper derives a lower bound on the number of and type of (single or multiwriter) variables that a mutual exclusion algorithm must use in order to be correct for PC-G. Specifically, any such solution for n processes must use at least one multiwriter variable and n single-writer variables. Peterson's algorithm for two processes uses one multiwriter and two single-writer variables, and therefore establishes that this bound is tight for two processes. This paper presents a new n-process algorithm for mutual exclusion that is correct for PC-G and achieves the bound for any n. While Peterson's algorithm is fair, this extension to arbitrary n is not fair. Six known algorithms that use the same number and type of variables are shown to fail to guarantee mutual exclusion when the memory consistency model is only PC-G, as opposed to the sequential consistency model for which they were designed. A corollary of our investigation is that, in contrast to sequential consistency, multiwriter variables cannot be implemented from single-writer variables in a PC-G system

No abstract available.

Finding a maximal or maximum matching in a graph is a well-understood problem for which efficient sequential algorithms exist. Applications of matchings in distributed settings make it desirable to find self-stabilizing asynchronous distributed solutions to these problems. We first present a self-stabilizing algorithm for finding a maximal matching in a general anonymous network under read/write atomicity with linear round complexity. This is followed by a self-stabilizing algorithm, with quadratic time complexity, for finding a maximum matching in a bipartite network under composite atomicity. These results represent significant progress in the area of distributed algorithms for matchings.

Weakening the memory consistency model of a multiprocess system improves its performance and scalability. However, these models sacrifice programmability because they create complex behaviors of shared memory. Without the use of expensive, built-in synchronization, these models exhibit poor capabilities to support solutions for fundamental process coordination problems [2]. This leads programmers to aggressively use these forms of synchronization, incurring additional performance burdens on the system. A multiprocessor system constructed from SPARC v8 [6] processors is one example of a system with weak memory consistency.

In a network of asynchronous processors, the cost to send a message can differ significantly from one communication link to another. In such a setting, it is desirable to factor the cost of links into the cost of distributed computation. Assume that associated with each link is a positive weight representing the cost of sending one message along the link, and the cost of an algorithm executed on a weighted network is the sum of the costs of all messages sent during its execution. We determine the asymptotic complexity of distributed leader election on a weighted unidirectional asynchronous ring assuming this notion of cost, by exhibiting a simple algorithm and a matching lower bound for the problem for any collection of edge weights. As a consequence, we see that algorithms designed for unweighted rings are not in general efficient for the weighted case.

A model that captures communication on asynchronous unidirectional rings is formalized. Our model incorporates both probabilistic and nondeterministic features and is strictly more powerful than a purely probabilistic model. Using this model, a collection of tools are developed that facilitate studying lower bounds on the expected communication complexity of Monte Carlo algorithms for language recognition problems on anonymous asynchronous unidirectional rings. The tools are used to establish tight lower bounds on the expected bit complexity of the Solitude Verification problem that asymptotically match upper bounds for this problem. The bounds demonstrate that, for this problem, the expected bit complexity depends subtly on the processors' knowledge of the size of the ring and on whether or not processor-detectable termination is required.

The inherent bit complexity of leader election on asynchronous unidirectional rings of processors is examined under various assumptions about global knowledge of the ring. If processors have unique identities with a maximum of m bits, then the expected number of communication bits sufficient to elect a leader with probability 1, on a ring of (unknown) size n is $O(nm)$. If the ring size is known to within a multiple of 2, then the expected number of communication bits sufficient to elect a leader with probability 1 is $O(n\log n)$. These upper bounds are complemented by lower bounds on the communication complexity of a related problem called solitude verification that reduces to leader election in $O(n)$ bits. If processors have unique identities chosen from a sufficiently large universe of size s, then the average, overall choices of identities, of the communication complexity of verifying solitude is $\Omega (n\log s)$ bits. When the ring size is known only approximately, then $\Omega (n\log n)$ bits are required for solitude verification. The lower bounds address the complexity of certifying solitude. This is modelled by the best-case behaviour of nondeterministic solitude-verification algorithms.

Article Probabilistic solitude verification on a ring Share on Authors: Karl Abrahamson Department of Computer Science, University of British Columbia, Vancouver, British Columbia Department of Computer Science, University of British Columbia, Vancouver, British ColumbiaView Profile , Andrew Adler Department of Mathematics, University of British Columbia, Vancouver, British Columbia Department of Mathematics, University of British Columbia, Vancouver, British ColumbiaView Profile , Lisa Higham View Profile , David Kirkpatrick View Profile Authors Info & Claims PODC '86: Proceedings of the fifth annual ACM symposium on Principles of distributed computingNovember 1986 Pages 161–173https://doi.org/10.1145/10590.10604Online:01 November 1986Publication History 17citation164DownloadsMetricsTotal Citations17Total Downloads164Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access