Full stack (both server-side and client-side) web application development has become one of the primary forms of software development. Consequently, our students should develop skill in software engineering within this context. This presents a challenge because multiple frameworks and languages need to be used, they are rapidly changing, and the programming styles that are important (such as functional programming and event-driven programming) are non-trivial and often new to students. Here we provide a preliminary report on a course that addresses this challenge by being both a first course in a software engineering sequence and an introduction to full stack web application development using current technologies. The course is the third course in the curriculum of a computer science major.

Our students' reading comprehension skills underpin their ability to learn the concepts and competencies in computer science. However, there has been little attention given to evaluating how well our students comprehend what they read and the effectiveness of strategies to improve their reading comprehension. In this paper we focus on the case of a non-major course on internet ethics and the reading of the original writings of key figures in ethical theory. Due to the observed weakness of the reading comprehension skills of the students, we have been teaching our students strategies to improve their skills in reading comprehension and meta-comprehension within the framework of an in-class group reading. The reading strategies we have been using are described, evaluated, and placed in the context of the reading comprehension literature. Increased awareness of the limitations of the reading comprehension skills of our students and of ways to teach the students strategies to improve those skills should prove useful in helping instructors ensure that our students have the foundation they need to be successful in their computer science studies.

Computer system subjects ranging from computer organization and operating systems to computer networking and database systems form an integral part of a computer science or computer engineering major. Because the subjects are usually taught as separate courses, students may not recognize that they share many design principles. We identify a set of these principles and demonstrate how they apply to all these aspects of a computer system. In our experience, students' understanding of these subjects and how they are inter-related improves when we identify and illustrate these common principles.

Traditional coverage of network programming techniques in a computer networking course addresses sockets, remote procedure call, and object-oriented remote procedure call. We propose two innovations to that coverage. The first is to emphasize the historical development of those techniques as a sequence with each technique evolving from the previous one. The second innovation is to extend the historical development and the techniques to the important current technique of web services.

This paper describes the experiences of teaching a new undergraduate grid computing course to students across the State of North Carolina in Fall 2004. This course is specifically focused at the undergraduate level and has a large number of geographically distributed participating sites. New materials have been developed for undergraduate students. We have developed a coherent set of grid computing programming assignments. All the materials developed are available on-line. This course also had internationally known guest speakers to provide state-of-the art presentations. Apart from developing grid computing materials, a number of issues arose in using the grid computing software and coordinating the activities, which are described here.

Grid computing is now mature enough and important enough to be studied as a full course at the undergraduate level for upper-level computer science majors. We have developed such a course, including a set of lecture slides, assignments, and assignment handouts specifically targeted for this audience. The sequence of assignments is a key part of the course. Some of the assignments are modifications of pre-existing work and others are completely new. We describe the key decisions we made about the course organization and content and describe the assignments. An important feature of the course is that it was geographically distributed with copies of the grid software installed at three campuses. Those campuses plus three others were receiving sites and included students and faculty associated with nine universities.

Understanding the execution of an object-oriented program can be a challenge for a student starting a CS1 course. We believe that a type of diagram that we call a memory diagram can aid the student in understanding object-oriented programming and can assist the instructor in assessing the student's understanding.Memory diagrams focus on how, in an abstract sense, the memory of the machine changes as the program executes. Though memory diagrams are a simple idea, by careful use of shape and placement, a number of key points about the meaning of a program fragment can be conveyed visually. We have found a correlation between a student's ability to construct these diagrams and that student's comprehension of object-oriented concepts. We feel that this correlation indicates that memory diagrams can be used as an assessment technique that, in turn, can be used to improve student learning.

A number of the key concepts in the design of computer networks lend themselves to illustration through animation. Animation can make the main features of these concepts accessible to the beginning undergraduate student as well as to more advanced students. We have identified six of these networking concepts: packet encapsulation; packet fragmentation; error control; media access in Ethernet local-area networks; domain name resolution; and the hypertext transfer protocol. We developed Java applets and accompanying materials to illustrate four of these concepts. The applets serve two roles: one role as a visual representation of different scenarios with respect to the concept in question; the second role as a vehicle for experimentation. We discuss the applets, the sequence of points each applet is designed to convey, and how the user can conduct experiments to further understand the networking concept. For the other two concepts, we show how the student can use free, easily available software to observe how the concept is implemented in the Internet.

As the complexity and variety of computer system hardware increases, its suitability as a pedagogical tool in computer organization/architecture courses diminishes. As a consequence, many instructors are turning to simulators as teaching aids, often using valuable teaching/research time to construct them. Many of these simulators have been made freely available on the Internet, providing a useful and time-saving resource for other instructors. However, finding the right simulator for a particular course or topic can itself be a time-consuming process. The goal of this paper is to provide an easy-to-use survey of free and Internet-accessible computer system simulators as a resource for all instructors of computer organization and computer architecture courses.

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The introductory operating systems course has a tendency to appear to the student as a disparate collection of topics such as synchronization primitives, process scheduling algorithms, and page replacement policies. We describe a sequence of material to cover early in the operating systems course that prevents this tendency by clarifying the goal of the course and by providing a framework for understanding how the later course material is used in kernel design. The material centers around two concepts. First is the importance of the abstraction provided by the system call interface, that the kernel is the implementation of that interface, and the analogy with the instruction set interface the student has already encountered. Second is how the interrupt vector mechanism in a broad sense is central to how the kernel functions and underpins the actual implementation of many of the other topics in the course. Illustration through code from a real operating system kernel is a key feature of how this sequence makes clear the workings of an operating system.

Investigates the performance of word-packet, slotted unidirectional ring-based hierarchical direct networks in the context of large-scale shared memory multiprocessors. Slotted unidirectional rings are attractive because their electrical characteristics and simple interfaces allow for fast cycle times and large bandwidths. For large-scale systems, it is necessary to use multiple rings for increased aggregate bandwidth. Hierarchies are attractive because the topology ensures unique paths between nodes, simple node interfaces and simple inter-ring connections. To ensure that a realistic region of the design space is examined, the architecture of the network used in the Hector prototype is adopted as the initial design point. A simulator of that architecture has been developed and validated with measurements from the prototype. The system and workload parameterization reflects conditions expected in the near future. The results of this study shows the importance of system balance on performance.>

The class of NUMA (nonuniform memory access time) shared memory architectures is becoming increasingly important with the desire for larger scale multiprocessors. In such machines, the placement and movement of code and data are crucial to performance. The operating system can play a role in managing placement through the policies and mechanisms of the virtual memory subsystem. In this paper, we develop an analytic model of memory system performance of a Local/Remote NUMA architecture based on approximate mean-value analysis techniques. The model assumes that a simple workload model based on a few parameters can often provide insight into the general behavior of real applications. The model is validated against experimental data obtained with the DUnX operating system kernel for the BBN GP1000 while running a synthetic workload. The results of this validation show that in general, model predictions are quite good, though in some cases the model fails to include the effect of unexpected behaviors in the implementation. Experiments investigate the effectiveness of dynamic multiple-copy page placement. We investigate the cost of incorrect policy decisions by introducing different percentages of policy error and measuring their effect on performance.

For given input the global trace generated by a parallel program in a shared memory multiprocessing environment may change as the memory architecture, and management policies change. A method is proposed for ensuring that a correct global trace is generated in the new environment. This method involves a new characterization of a parallel program that identifies its address change points and address affecting points. An extension of traditional process traces, called the intrinsic trace of each process, is developed. The intrinsic traces maximize the decoupling of program execution from simulation by describing the address flow graph and path expressions of each process program. At each point where an address is issued, the trace-driven simulator uses the intrinsic traces and the sequence of loads and stores before the current cycle, to determine the next address. The mapping between load and store sequences and next addresses to issue, sometimes, requires partial program reexecution. Programs that do not require partial program reexecution are called graph-traceable.>

Dynamic page placement policies for NUMA (nonuniform memory access time) shared-memory architectures are explored using two approaches that complement each other in important ways. The authors measure the performance of parallel programs running on the experimental DUnX operating system kernel for the BBN GP1000, which supports a highly parameterized dynamic page placement policy. They also develop and apply an analytic model of memory system performance of a local/remote NUMA architecture based on approximate mean-value analysis techniques. The model is validated against experimental data obtained with DUnX while running a synthetic workload. The results of this validation show that, in general, model predictions are quite good. Experiments investigating the effectiveness of dynamic page-placement and, in particular, dynamic multiple-copy page placement the cost of replication/coherency fault errors, and the cost of errors in deciding whether a page should move or be remotely referenced are described.>

We address the problem of paged main memory management in the local/remote architecture subclass of shared memory multiprocessors. We consider the case where the operating system has primary responsibility and uses page migration as its main tool. We identify some of the key issues with respect to architectural support (reference history maintenance, and page size), and operating system mechanism (duration between daemon passes, and number of migration daemons).

We conjecture that a paged memory with page migration by the operating system may be an effective system environment for a local/remote shared memory architecture executing a single parallel computation. Implementing a paged memory in such an architecture raises several issues with respect to page table management. These issues include page table placement, page table replication level, and page table storage overhead. We discuss these issues, propose alternative solutions, and present an experimental evaluation of the solutions.

Exact results are given for the processing power in a multibus multiprocessor with constant memory cycle times and geometric interrequest times. Both uniform and nonuniform memory accesses are considered. Such results have not previously been obtained. In order to derive these results we use a method of introducing time into Petri nets, called Generalized Timed Petri Nets (GTPN), that we have developed. We describe the GTPN and how it is applied to the multiprocessor interference question. We reach several new conclusions. A commonly used definition of processing power can lead to substantial underestimation of the true processing power of the system. If the real system has a constant memory access time and any number of buses, then assuming an exponential access time can lead to substantial errors when estimating processing power probability distributions. In multibus systems with only a few buses a critical memory interrequest time exists. Performance close to that with a crossbar is attainable when the interrequest time is larger than the critical value. Obtaining these results illustrates the advantages, for moderate size state spaces, of the GTPN over simulation with respect to both model design and running time.

We have developed a Generalized Timed Petri Net (GTPN) model for evaluating the performance of computer systems. Our model is a generalization of the TPN model proposed by Zuberek [1] and extended by Razouk and Phelps [2]. In this paper, we define the GTPN model and present how performance estimates are obtained from the GTPN. We demonstrate the use of our automated GTPN analysis techniques on the dining philosophers example. This example violates restrictions made in the earlier TPN models. Finally, we compare the GTPN to the stochastic Petri net (SPN) models. We show that the GTPN model has capabilities for modeling and analyzing parallel systems lacking in existing SPN models. The GTPN provides an efficient, easily used method of obtaining accurate performance estimates for models of computer systems which include both deterministic and geometric holding times.

We use an exact analytical technique, based on Generalized Timed Petri Nets (GTPNs), to study the performance of shared bus cache consistency protocols for multiprocessors. We develop a general framework within which the key characteristics of the Write-Once protocol and four enhancements that have been combined in various ways in the literature can be identified and evaluated. We then quantitatively assess the performance gains for each of the four enhancements. We consider three levels of data sharing in our workload models. One of the enhancements substantially improves system performance in all cases. Two enhancements are shown to have negligible effect over the range of workloads analyzed. The fourth enhancement shows a small improvement for low levels of sharing, but shows more substantial improvement as sharing is increased, if we assume a “good access pattern”. The effects of two architectural parameters, the blocksize and the main memory cycle time are also considered.