ABSTRACT As interest in social network studies has grown bigger along with the development of the Web, social network trust management and applications have come into the spotlight. The increasing interest in social network services that are open systems has motivated the need for a reliable trust model that enables practical information sharing and information protection. In this paper, we propose an identity management‐based social trust model for solving a sparsity problem and an information leakage. The proposed trust model contributes to increasing the opportunities for information sharing. In addition, the creation and use of identity groups with a clustering approach and partial identities in the proposed approach effectively address security and privacy risks in social networks. In experiments, the performance of the proposed approach is evaluated using precision–recall and F‐measures. Copyright © 2011 John Wiley & Sons, Ltd.

Abstract When a single video server provides a streaming service, there are many limitations. Thus, clusters of multiple video servers are widely used today to provide better service. How movies are allocated to each server in a cluster is an important and ongoing research topic because the movies are large, and there are so many of them. We have developed a movie allocation algorithm based on the observation that client accesses follow a Zipf distribution. We have developed an algorithm in which servers use their storage to their full capacities, movies are assigned to servers as evenly as possible, servers receive requests as evenly as possible, and all movies are allocated to at least one server. Copyright © 2010 John Wiley & Sons, Ltd.

Abstract This paper addresses performance issues on ARDA Metadata Grid Application (AMGA) and presents new techniques to improve the throughput of AMGA for the WISDOM environment. The first issue is a performance degradation problem when AMGA is used as a metadata service for task retrieval in the WISDOM environment. To deal with the issue, a new AMGA operation designed to reduce the communication overhead required to retrieve a task from AMGA is proposed. According to a performance study conducted with the new operation, the throughput of task retrieval using the proposed operation can be as much as 70 times higher than the throughput when using the existing AMGA operations. The second issue is an AMGA throughput issue in large‐scale grid‐enabled applications such as WISDOM, where it is not uncommon that thousands of jobs running on grid nodes access the AGMA service simultaneously. To address this issue, integration of a load‐balancing technique and a DB connection pool technique into the AMGA are proposed. Test results demonstrate that the performance can be improved linearly in proportion to the number of AMGA servers set up for load balancing; the performance improvement continues until the performance limit of the backend database system is reached. Copyright © 2009 John Wiley & Sons, Ltd.

The Cell BE processor is a heterogeneous multicore that contains one PowerPC Processor Element (PPE) and eight Synergistic Processor Elements (SPEs). Each SPE has a small software-managed local store. Applications must explicitly control all DMA transfers of code and data between the SPE local stores and the main memory, and they must perform any coherence actions required for data transferred. The need for explicit memory management, together with the limited size of the SPE local stores, makes it challenging to program the Cell BE and achieve high performance. In this paper, we present the design and implementation of our COMIC runtime system and its programming model. It provides the program with an illusion of a globally shared memory, in which the PPE and each of the SPEs can access any shared data item, without the programmer having to worry about where the data is, or how to obtain it. COMIC is implemented entirely in software with the aid of user-level libraries provided by the Cell SDK. For each read or write operation in SPE code, a COMIC runtime function is inserted to check whether the data is available in its local store, and to automatically fetch it if it is not. We propose a memory consistency model and a programming model for COMIC, in which the management of synchronization and coherence is centralized in the PPE. To characterize the effectiveness of the COMIC runtime system, we evaluate it with twelve OpenMP benchmark applications on a Cell BE system and an SMP-like homogeneous multicore (Xeon).

There have been strong demands for a fast and cycle-accurate virtual platforms in the embedded systems area where developers can do meaningful software development including performance debugging in the context of the entire platform. In this paper, we describe the design and implementation of a fast and cycle-accurate architecture simulator called FaCSim as a first step towards such a virtual platform. FacSim accurately models the ARM9E-S processor core and ARM926EJ-S processor's memory subsystem. It accurately simulates exceptions and interrupts to enable whole-system simulation including the OS. Since it is implemented in a modular manner in C++, it can be easily extended with other system components by subclassing or adding new classes. FaCSim is based on an interpretive simulation technique to provide flexibility, yet achieving high speed. It enables fast cycle-accurate architecture simulation by means of three mechanisms. First, it computes elapsed cycles in each pipeline stage as a chunk and incrementally adds it up to advance the core clock instead of performing cycle-by-cycle simulation. Second, it uses a basic-block cache that caches decoded instructions at the basic-block level. Finally, it is parallelized to exploit multicore systems that are available everywhere these days. Using 21 applications from the EEMBC benchmark suite, FaCSim's accuracy is validated against the ARM926EJ-S development board from ARM, and is accurate in a ±7% error margin. Due to basic-block level caching and parallelization, FaCSim is, on average, more than three times faster than ARMulator and more than six times faster than SimpleScalar.

In this paper, we suggest a simple but efficient solution for the Web service composition. When we search Web services for composition, we visit the service which gives the biggest number of new responses, because then there is a higher probability to invoke more other Web services. And also we suggest optimization techniques to get optimized composition result. Optimization processes consist of two phases: one is to remove unnecessary Web services and the other is to find the best starting point of a composition. Test results show that the proposed composing and optimization methods can compose Web services in optimal length in fast way.

In simultaneous multithreading (SMT) multiprocessors, using all the available threads (logical processors) to run a parallel loop is not always beneficial due to the interference between threads and parallel execution overhead. To maximize performance in an SMT multiprocessor, finding the optimal number of threads is important. This paper presents adaptive execution techniques to find the optimal execution mode for SMT multiprocessor architectures. A compiler preprocessor generates code that, based on dynamic feedback, automatically determines at run time the optimal number of threads for each parallel loop in the application. Using 10 standard numerical applications and running them with our techniques on an Intel 4-processor Hyper-Threading Xeon SMP with 8 logical processors, our code is, on average, about 2 and 18 times faster than the original code executed on 4 and 8 logical processors, respectively.

Web services following distributed object computing technology like DCOM, CORBA provides remote procedure call mechanism based on XML-based open standard such as SOAP, WSDL, and UDDI, and it is spotlighted as means of integration and collaboration at e-business. Especially, UDDI is the Web services registry enabling to register and search Web services that takes charge of providing infrastructure for Web services. However, the existing UDDI has a few problems that searching process is very simple and it cannot provide information of Web services quality and quality-based retrieval. Therefore, this study suggests improved UDDI model that evaluates the Web services quality and use this information for searching.

The off-line handwritten characters recorded on prescribed form documents may be overwritten by the lines of the form documents. Overwritten characters should be isolated in order to be recognized more effectively. However, removal of the lines causes breaks in the overwritten characters. Consequently, a character restoration process is necessary. In this paper, the shape types of overwritten characters are analyzed and a method of restoring characters that have been broken by line removal is proposed. A 97% correct restoration ratio was obtained through this method.

We suggest a new object-oriented functional language, OOId, which is based on a functional language Id and extended with object-oriented language features. We also discuss how to map OOId program onto DAVRID, which is a kind of multithreaded architecture based on the dataflow model. The comparison of execution time of two programs written in Id and OOId for the matrix multiplication problem, shows we can effectively run OOId program with just a little slow-down of execution time. In addition, the rate of slow-down is decreased, as the size of the matrix is larger. That means we can use good features of object-oriented language by paying just a little slow-down of execution time.

A 'class' in the object-oriented paradigm represents both interface and implementation of the class. However, interface and implementation of a class are needed for different purposes, since class interface is shared among most users, while class implementation is used only by the implementers of the class. The authors introduce a new level of data abstraction, called the 'class-implementation level', which is based on separate management of interface and implementation of a class. They also describe a new model for OODBMS which provides users with the abstract view of the class implementation.

C++ uses 'class' as the basis of 'subtype polymorphism' and 'inheritance', but it has been pointed out that the overloading of 'class' limits the expressiveness and makes its type system inflexible. This means that C++ and some other object oriented languages had to separate a class into two modules-an interface and an implementation. But, there seems to be no leading C++ model for separating the interface lattice from the implementation lattice. Moreover none of the proposed models describe the result of the separation in a formal way. As a result it is hard to understand what the type space would be like after the separation. The paper presents a formal model for the separation of interface and implementation in C++, and which explains the properties of the resulting type space after the separation.

Multithreaded architectures taking a hybrid approach of von Neumann computers and dataflow computers are recently in active research. Multithreaded architectures can improve the performance by the locality exploitation within threads and asynchronous parallel execution among threads. However, it has been overlooked how to exploit effectively the locality of large shared data structures among threads in multithreaded architectures. In this paper, we propose a new data structure, called IB-structure, which is an extension of I-structure to facilitate the distribution of data structure and exploit the locality of data structure, and implement it on multithreaded architecture DAVRID (DAtaflow Von Neumann RISC hybrID). The simulation results show that IB-structure is superior to I-structure over several benchmarks.

MPAs (massively parallel architectures) should address two fundamental issues for scalability: synchronization and communication latency. Dataflow architectures cause problems of excessive synchronization costs and inefficient execution of sequential programs while they offer the ability to exploit massive parallelism inherent in programs. In contrast, MPAs based on the von Neumann computational model may suffer from inefficient synchronization mechanism and communication latencies. DAVRID (Dataflow von Neumann, RISC Hybrid) is a massively parallel multithreaded architecture. By combining the advantages of the von Neumann model and the dataflow model, DAVRID preserves good single thread performance and tolerates latency and synchronization costs. We describe the DAVRID architecture and evaluate it through simulation results over several benchmarks.>

Multithreading has been much focused on as one of the strongest parallel instruction execution paradigms for massively parallel processing. In this paper, we describe the compilation processes of parallel programming language Id- for a multithreaded architecture DAVRID(DAtaflow Von Neumann RISC hybrlD). Two fundamental issues in parallel processing, tolerance to communication latency and inexpensive synchronization, are solved by a compiler-controlled multithreading. Our compiler features a simple mechanism for handling closures, and a loop unfolding technique for handling parallel and sequential loops in separate, which can greatly contribute to parallel execution of loops.

No abstract available.

In most multithreaded node architectures moti- vated by the dataflow computational model, spatial parallelism could not be exploited at the thread level due to the resource deficit incurred by their inter nal organization. So we proposed a node architecture exploiting both spatial and temporal parallelism of a program. A multi-port non-blocking data cache is in corporated into our design to cope with the excessive data bandwidth required in parallel execution of mul tiple threads. The proposed node architecture may contribute to greatly reducing communication latency through the interconnection network. Simulation re sults show that parallel loops can be executed on this architecture more efficiently than on other competi tive ones.

The Timing Drive Placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.

We develop two fast algorithms for the layering problem that arises when the single-row routing approach to wire layout is used. Both of these algorithms are for the case when the upper and lower street capacities are two. While neither of these algorithms guarantees the production of an optimal layering, it has been empirically determined that both will produce better layerings than an earlier proposed algorithm [13] for this problem. In addition, our algorithms run much faster than the earlier algorithm.

We develop two fast algorithms for the layering problem that arises when the single row routing approach to wire layout is used. Both these algorithms are for the case when the upper and lower street capacities are two. While neither of these algorithms guarantees to produce an optimal layering, both are empirically determined to produce better layerings than an earlier proposed algorithm for this problem. In addition, our algorithms run much faster than the earlier algorithm.

We develop fast linear time algorithms for single row routing when the upper and lower street capacities are less than or equal to three. A similarly fast algorithm is developed for the case when one of the streets has a capacity 1 and the other has an arbitrary capacity. Experimental results show that our algorithms are many times faster than previously developed algorithms.