Privacy in Vehicular Ad-hoc NETworks (VANETs) is one of the most important issues to attract users to this new technology. In this paper we propose a novel protocol that allows vehicles using the same application in a VANET to agree on an encryption key to exchange confidential data while preserving the privacy. We do this by combining the Elliptic Curve Integrated Encryption Scheme (ECIES) with ring signatures and we evaluate the protocol with respect to the privacy of the vehicle. These results clearly demonstrate that the privacy of vehicles can be preserved while reducing considerably the number of necessary pseudonyms in comparison to exploiting ECIES only.

Active-safety features in vehicles are enabled by a multitude of different kinds of sensors such as acceleration sensors, radars, or cameras. Apart from the systems which use these sensors also service providers are interested in the data produced by these sensors and the corresponding geographical position. These data can be utilized for instance in order to, e.g., increase the quality of street maps data for automated driving. However, a service provider may also abuse this information to create precise movement profiles of the vehicles. In order to prevent a provider from creating such profiles, we introduce path hiding strategies for vehicles equipped with vehicle-to- vehicle (V2V) communication. This approach is a powerful means to protect the privacy of the driver. We propose in the sequel two strategies on how to exchange the data for privacy enhancement. For assessment purposes, we compare the efficiency of our strategies by means of simulation and evaluate their results from a large application scenario. Furthermore, we give a recommendation on the best strategy. Conclusively, we demonstrate that the approach of exchanging sensor readings with other vehicles prior to an upload operation prevents the creation of movement profiles by a central entity such as a service provider.

Vehicles in Vehicular Ad-Hoc NETworks (VANETs) use applications which require an exchange of application-specific confidential data between vehicles. This data must be protected from vehicles not using the application. To achieve this, the vehicles have to authenticate each other in a way that the other communication partner is convinced that the vehicle is eligible to exchange the data. Furthermore, both partners have to agree on an encryption key. This kind of protocols is known as approaches to authenticated key agreement. The proprietary protocol implemented and evaluated in this paper supports these properties and, in addition, preserves the privacy of the vehicles. After executing the protocol, neither one of the participating vehicles nor an eavesdropping third vehicle in communication range can unveil the identity of the vehicles. This important property is achieved by combining the Elliptic Curve Integrated Encryption Scheme (ECIES) with ring signatures. Furthermore, we demonstrate how this protocol can be applied within a GeoNetworking message. We present a prototype of the protocol and discuss evaluation results produced from a test setup with real vehicles. The results show that a feasible ring size can be established to reliably protect the privacy of the vehicles. We also analyse the execution time of the complete protocol, of the constituent protocol steps as well as of the different components like security and transmission. The presented results clearly show that the protocol can be completed on time, even when the communicating vehicles have a high relative velocity and poor communication range.

Multiprocessor system-on-chip (MPSoC) architectures are a huge challenge in embedded system design. This situation arises from the fact that available MPSoCs and related designs flows are not tailored to the specific needs of embedded systems. This work demonstrates how to provide self-healing properties in embedded MPSoC design. This is achieved by combining the features of a generic approach to create virtualizable MPSoCs out of off-the-shelf embedded processors with a methodology to derive system configurations, such as task-processor bindings, which are optimal in terms of safety and execution time. The virtualization properties enable a reshaping of the MPSoC at runtime. Thus, system configurations may be exchanged rapidly in a dynamic fashion. As a main result of this work, embedded multiprocessor systems are introduced, which dynamically adapt to changing operating conditions, possible module defects, and internal state changes. We demonstrate the figures of merit of such reconfigurable MPSoC embedded systems by means of a complex automotive application scenario mapped to an FPGA featuring a virtualizable array of eight soft-core processors.

Advanced driver-assistance systems (ADASs) employ single-object information to provide safety, comfort, or infotainment features. While today's systems use common sensors, such as radars or cameras, to recognize and predict the future states of relevant traffic participants, next-generation ADASs will also use data from additional sources such as Car-to-X (C2X) communication networks. We present a method that uses information on other traffic participants and furthermore recognizes and considers their interactions in terms of traffic maneuvers. For this purpose, a probabilistic approach is presented, which identifies object interactions and different road characteristics. This method may find a particular application in the C2X domain for evaluating the mobility of neighboring vehicles based on received messages. In this paper, we present M aneuver Assessment For R eliable Verification of C2X mobility data (MARV-X), which is a tool embodying a two-stage process for reliable C2X mobility data verification. The first stage consists of a dedicated mobility estimator realized by a Kalman filter (KF). In the second stage, a plausibility check for highly dynamic traffic situations is applied using the advocated probabilistic traffic maneuver recognition. MARV-X is fully integrated into the vehicle's C2X architecture. Its effectiveness is demonstrated by means of extensive real-world experiments.

At the cutting edge of today's security research and development, the SHA-3 competition evaluates a new secure hashing standard in succession to SHA-2. The five remaining candidates of the SHA-3 competition are BLAKE, Grøstl, JH, Keccak, and Skein. While the main focus was on the algorithmic security of the candidates, a side channel analysis has only been performed for BLAKE and Grøstl [1]. In order to equally evaluate all candidates, we identify side channel attacks on JH-MAC, Keccak-MAC, and Skein-MAC and demonstrate the applicability of the attacks by attacking their respective reference implementation. Additionally, we revisit the side channel analysis of Grøstl and introduce a profiling based side channel attack, which emphasizes the importance of side channel resistant hash functions by recovering the input to the hash function using only the measured power consumption.

This paper addresses the software transformation part of a comprehensive hardware/software co-design flow for the Discrete Event System Specification Model of Computation. The transformation methodology of such timed abstract models into embedded systems source code is the main contribution of this paper. Furthermore, the integration of legacy source code and communication interface instantiation is detailed. Thus, the advocated approach allows to reuse legacy source code within a hardware/software co-design flow based on model transformations. The feasibility of the approach is demonstrated by means of a realistic distributed real-time application example.

Dynamic partial reconfiguration allows the exchange of hardware configurations on FPGAs at run-time. Within a reconfigurable system that supports several different modules, resource requirements for interconnect between these modules may be considerably high. Enabling communication via a crossbar may require too many resources. State-of-the-art modelling methods for partial dynamic reconfiguration already support the fine-grained description of interaction between the partial modules. We propose both an online and an offline method for automatically generating interconnect according to such communication constraints, aiming at a low resource usage. The online algorithm determines an appropriate port assignment for the partial modules by means of a greedy approach and exploits port overlaps. The offline algorithm employs simulated annealing in order to find a proper port assignment and also incorporates the scheme for exploiting port overlaps. Constraint-generated interconnect requires significantly less resources than a crossbar, even if only a random port assignment is used. Proper port assignment by the online method reduces these requirements by an additional 10%, and using the offline method reduces them by an additional 30% on average. Online port assignment is faster than the offline method by several orders of magnitude. The interconnect generation tool introduced in this work takes textual input of communication constraints and automatically generates a corresponding hardware description in VHDL.

This paper performs an investigation into the security of Xilinx FPGA bitstreams, introducing a tool-chain for reversing bitstreams back to their device-specific netlists. Bitstream reversal is performed by querying a database containing the mapping of bitstream bits to their related configurable FPGA resources and a secondary database describing the FPGA structure. The mapping database is created by applying an algorithm that correlates binary bitstream data with data extracted from a corresponding netlist. The resource database is derived from a textual device description which can be obtained from the Xilinx design flow. The method can successfully reverse certain sections of the bitstream, although complete bitstream reversal remains infeasible for the time being. The presented tool-chain, the Bitfile Interpretation Library (BIL), improves on previous attempts at bitstream reverse engineering. It is made available as open source for further development.

In the recent decade methods and applications of side-channel analysis gain more and more attention for industry applications as well as in academia. The research on counter-measures against power analysis attacks on embedded devices with security-sensitive applications turned out to be a challenging area. Very often the proposed countermeasures consume to much resources in order to increase the barrier to hinder a successful attack. The presented scheme uses randomized isomorphisms of the algebraic construction of the S-box and thus increases the resistance at a very low cost in terms of hardware resources. The resource utilization of the proposed masking scheme is smaller than a standard Boolean masking scheme for FPGAs. Our conducted experiments on the FPGA evaluation platform SASEBO GII demonstrates that we improved the resistance against the common DPA attack about 100 times compared to the non-hardened AES-128 version.

Advanced Driver Assistance Systems (ADAS) employ single object information to provide safety, comfort, or infotainment features. The required data is mainly extracted from external sensors to recognize and predict the future states of relevant traffic participants. Next generation ADAS will also use data from additional sources like, e.g., Car-to-X communication networks, to avoid some typical restrictions of common sensor setups. In this work, we present a method, which uses information on other traffic participants, and furthermore recognizes and considers their interactions in terms of traffic maneuvers to better predict their states. For this purpose, a probabilistic framework is presented, which recognizes object interactions as well as different road characteristics by introducing local, adaptive occupancy grids. The resulting maneuver recognition is shown to considerably improve received mobility data in terms of position, speed, and heading. These concepts have been fully implemented and evaluated by means of real world experiments.

Dynamic partial reconfiguration enables the reconfiguration of hardware devices at run-time, which saves resources, but introduces additional design complexity. Various methods exist for the specification of reconfiguration schedules, which are either too simple for the description of complex processes, or are inherently difficult to verify. We employ a variant of the π-calculus for modelling dynamic partial reconfiguration. The π-calculus is a process algebra originally constructed for modelling communicating systems, but can be repurposed as a scheduling method for dynamic partial reconfiguration on FPGA devices. In order to apply this type of scheduling for the design of hardware systems, it has to be determined how to allocate the scheduled tasks on the device. By use of a verification tool for the π-calculus, constraints can be extracted from a given system specification. These constraints form the basis to derive the placement of the reconfigurable areas in an automatic fashion.

Trusted computing is gaining an increasing acceptance in the industry and finding its way to cloud computing. With this penetration, the question arises whether the concept of hard-wired security modules will cope with the increasing sophistication and security requirements of future IT systems and the ever expanding threats and violations. So far, embedding cryptographic hardware engines into the Trusted Platform Module (TPM) has been regarded as a security feature. However, new developments in cryptanalysis, side-channel analysis, and the emergence of novel powerful computing systems, such as quantum computers, can render this approach useless. Given that, the question arises: Do we have to throw away all TPMs and loose the data protected by them, if someday a cryptographic engine on the TPM becomes insecure? To address this question, we present a novel architecture called Sustainable Trusted Platform Module (STPM), which guarantees a secure update of the TPM cryptographic engines without compromising the system's trustworthiness. The STPM architecture has been implemented as a proof-of-concept on top of a Xilinx Virtex-5 FPGA platform, demonstrating a test case with an update of the fundamental hash engine of the TPM.

Trusted computing is gaining an increasing acceptance in the industry and finding its way to cloud computing. With this penetration, the question arises whether the concept of hard-wired security modules will cope with the increasing sophistication and security requirements of future IT systems and the ever expanding threats and violations. So far, embedding cryptographic hardware engines into the Trusted Platform Module (TPM) has been regarded as a security feature. However, new developments in cryptanalysis, side-channel analysis, and the emergence of novel powerful computing systems, such as quantum computers, can render this approach useless. Given that, the question arises: Do we have to throw away all TPMs and loose the data protected by them, if someday a cryptographic engine on the TPM becomes insecure? To address this question, we present a novel architecture called Sustainable Trusted Platform Module (STPM), which guarantees a secure update of the TPM cryptographic engines without compromising the system's trustworthiness. The STPM architecture has been implemented as a proof-of-concept on top of a Xilinx Virtex-5 FPGA platform, demonstrating a test case with an update of the fundamental hash engine of the TPM.

The π-calculus is a process algebra originally designed for modelling communicating systems. In this work, it is applied to the design of schedules for partial dynamic reconfiguration, which denote when modules become active and which channels they use for communication. While the execution of the π-calculus in software is possible, a direct execution in hardware is desirable for two reasons: Firstly, direct hardware execution removes the requirement to use a softcore processor. As will be shown in this paper, π-calculus processes only have a tiny hardware footprint. Secondly, the π-calculus is inherently concurrent, and its execution on dedicated hardware can thus be greatly accelerated. This can be used in order to speed up the simulation of schedules. The acceleration of π-calculus simulation may have applications in other fields, since the π-calculus has been used for modelling systems in a wide range of disciplines, for instance in computational biology. The paper shows how π-calculus primitives can be translated into corresponding hardware modules. Since this is difficult to do manually, a tool was created which automatically maps complete processes into synthesizable VHDL code.

For Car-to-X (C2X) communication, group signature based protocols can provide privacy and authentication for vehicles that are members of the respective group. Current group approaches all rely on a centralized group key generation and distribution. We propose a novel decentralized approach based on n-party Diffie-Hellman key establishment. The proposed protocol implies a low latency for key establishment and a high robustness towards possible failures of single nodes. Simulations have been carried out to evaluate privacy enhancements of the proposed protocol in presence of a global passive adversary.

Field-programmable gate arrays (FPGAs) provide a means to massively parallelize computations. In order to make more efficient use of FPGA devices, the method of partial dynamic reconfiguration can be applied: By means of this approach, the FPGA configuration is updated at run-time so that the device can feature new functionality. If multiple stakeholders make use of the same device, it has to be ensured that confidential information cannot be leaked between these parties. Therefore, all feasible hazards of illicit information flow need to be taken into account. In this work, partial dynamic reconfiguration is scheduled using the π-calculus, a process algebra. Within the presented framework, a variant of the π- calculus is employed to activate and deactivate partial modules and to rearrange their interconnect. The modules employed by different stakeholders use ports for communication, for which valid targets of information flow can be defined. By means of formal verification, it is evaluated whether the information flow between functional units of the stakeholders proceeds according to the specification. Using a set of analysis rules, an associated tool can verify whether a given reconfiguration schedule ensures secure information flow.

This paper presents a state optimization approach within the Discrete Event System Specification Model of Computation. The goal of state optimization is to significantly soften the timing requirements of the model when transformed to a hardware implementation. The algorithm presented relocates the behaviour of zero-timeout states into adjacent states. Thus, the resulting model has much better timing properties, which considerably increase the amount of suitable target hardware architectures. The feasibility of the approach is demonstrated by means of a complex Digital Visual Interface controller application example.

Side-channel attacks have changed the design of secure cryptographic systems dramatically. Several published attacks on implementations of well known algorithms such as, e.g., AES, show the need to consider these aspects to build more resistant cryptographic systems. On the other hand, with the increasing use of cryptography in embedded systems a significant demand exists for cryptographic algorithms that are both resource-and power-efficient. These can be either modified existing or completely new ones. One of the candidates for such a new algorithm is the Tree Parity Machine Public Key Exchange, an algorithm based on artificial neural networks. While it has been evaluated in a number of practical applications in the past, its side-channel resistance has not been examined yet. We would like to close this gap and present a side-channel attack strategy as well as results gathered from measurements made on a real implementation.

Self-healing systems can restore their original functionality by use of run-time self-reconfiguration, a feature supplied by state of the art FPGA devices. Commonly, integrity checks are performed by reading back the device configuration and validating its hash value. Systems which are prone to tampering and piracy of intellectual property may disable configuration readback, which renders this method infeasible. We propose to secure systems by use of test vectors, requiring a certain system input sequence to always generate the same system output. The presented security mechanism is hard to tamper with and does not interfere with normal system operation. Although the required hardware overhead may be high in general, we show that the overhead can be kept relatively low if the method is applied only to select parts of the system, without any detrimental effect to the level of security that our mechanism provides. The mechanism is introduced into VHDL code using an automatic process. This approach to self-test and self-healing has been implemented on a Xilinx Virtex-5 device.

In this paper we present a secure micro kernel architecture (called Ray) that was designed from scratch with security goals in mind. It features some traditional security aspects like process isolation, advanced non-standard security aspects like padded non-readable memory boundaries and new contributions like memory gifts and behaviour deviation detection. This theoretical design has been implemented as a proof of concept for x86 based processors including a small set of essential drivers and user land applications in order to verify and test the claims made herein.

In this paper we propose a new approach to enhance security and privacy in C2X communication directly on the physical layer. Instead of using a single omni-directional antenna, our approach relies on an uniform linear antenna array, which enables beam forming. By this means, our approach allows adjusting the radiation and the reception patterns of the vehicle, which is essential for excluding undesired communication parties trying to eavesdrop exchanged messages or to distribute corrupted information. To specify the antenna array configuration appropriate to some important use cases, a simulation-based approach is deployed. A dedicated simulator is exploited, which produces field patterns and visualizes them according to a mobility model and on user settings. Based on the visual simulation results the antenna array has been specified and evaluated.

Beamforming is an approach for enhancing security and privacy in C2X communication. In this demo paper we describe a simulation tool for adaptive beamforming in the context of car-to-car and car-to-infrastructure communication. Besides verification, this simulator helps a system designer in specifying the antenna array in terms of element number, spacing, and phasing. The simulator determines the appropriate radiation pattern based on an embedded mobility model, a road map, and user settings.

Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universität Darmstadt, and is intended for instructors aiming to introduce a new course in reconfigurable computing. Therefore, a detailed description of the course structure and content is provided. In contrast to courses on digital system design, which use FPGAs as a case platform, our course places this platform at the center of its focus and highlights its features as a basis for reconfigurable computing. Both declarative knowledge and functioning knowledge are considered in defining learning outcomes based on a novel What-Why-How Model. Lab activities were designated to deepen the functioning knowledge. The written exam is aligned to learning outcomes and shows that most students acquired the intended outcomes.

The McEliece public-key cryptosystem relies on the NP-hard decoding problem, and therefore, is regarded as a solution for postquantum cryptography. Though early known, this cryptosystem was not employed so far because of efficiency questions regarding performance and communication overhead. This paper presents a novel processor architecture as a high-performance platform to execute key generation, encryption, and decryption according to this cryptosystem. A prototype of this processor is realized on a reconfigurable device and tested via a dedicated software interface. A comparison with a similar software solution highlights the performance advantage of the proposed hardware solution.

McEliece scheme represents a code-based public-key cryptosystem. So far, this cryptosystem was not employed because of efficiency questions regarding performance and communication overhead.This paper presents a novel processor architecture as a high-performance platform to execute key generation, encryption and decryption according to this cryptosystem. A prototype of this processor is realized on Virtex-5 FPGA and tested via a software API. A comparison with a similar software solution highlights the performance advantage of the proposed hardware solution.

This paper describes a systematic approach to integrate the Discrete Event Specified System (DEVS) methodology into SystemC. It thus combines Model of Computation (MoC) specific properties and the features of an advanced SystemC environment. The execution of abstract system level DEVS models is comparable to pure SystemC models and is significantly faster compared to other DEVS environments. Thus, system level models based on abstract MoCs may easily be executed in a SystemC environment. The proposed integration is realized as a non-introspective extension to the SystemC 2.2 kernel. The DEVS models are implemented on an additional software layer above the SystemC simulation kernel. Our approach may be used simultaneously with other layered extensions, e.g., SystemC-AMS or TLM.

Embedded systems aimed for applications in the IT security domain are characterized by specific needs in terms of computing power. The high computational loads stem both from algorithms, which have to address different symmetric and especially asymmetric encryption schemes such as AES, RSA, ECC and PBC, and from associated key size values ranging from 100's to several 1000's bits.

Group key management is a critical task in secure multicast applications such as Pay-TV over the Internet. The communication group key must be updated and distributed after every change in the group membership. Many solutions have been proposed in the last years to minimize the cost of this rekeying process on the server side. Most of these solutions are tree-based approaches such as the logical key hierarchy. These approaches suffer from three problems. First, tree-based solutions aim at minimizing rekeying costs only by reducing the number of needed cryptographic operations such as encryption or secure hashing. Second, these solutions do not treat the time-consuming digital signing needed to authenticate rekeying messages. Third, tree-based approaches manage huge amounts of keys by software which compromises security. In this paper, a novel hardware/software architecture is proposed, which optimizes the rekeying performance not only by minimizing the number of cryptographic operations, but also by reducing the execution times of these operations including digital signing with the aid of hardware acceleration. All help-keys are generated, managed, and stored on hardware, which enhances the system security. To keep flexibility, control-intensive tasks such as tree management are performed as software functions on the embedded processor. The presented rekeying processor is designed based on a comprehensive security analysis with the aid of a novel illustration for security threats, requirements, and technical solutions, a so-called security Y-diagram. A performance measurement on a prototype implementation shows that the rekeying processor can join and disjoin members much faster than software solutions besides supporting much larger groups.

The objective of this paper is to introduce a novel representation as a means to consider both permanent and temporal errors in order to increase the overall reliability of an embedded system. The deployment of embedded systems in safety critical applications, e.g. in the automotive domain, demands that the fundamental set of design criteria consisting of functionality, timeliness, and production costs be extended to consider of reliability as an optimization criterion. Thus reliability engineering becomes part of the overall design flow for embedded systems. The proposed approach is based on the introduction of permanent/transient error decision diagrams and on dedicated algorithms for the generation of system implementation sets which feature maximum reliability at minimal costs in terms of redundant resources. The proposed approach is demonstrated for a control system taken from the automotive domain.

Symmetric encryption, secure hashing, and random number generation are essential operations for many cryptographic applications. Realizations of these functions usually aim for high computational speed. For some applications, however, low resource usage is more important. Thus, this work presents a compact design for symmetric encryption, hash function, and Cryptographically Secure Random Number Generator. Its central element is a small AES-module, which is shared by all operations, leading to a lower resource usage than aggregated stand-alone solutions in previous work.

While a vast number ofsolutions to multicast group rekeying were published in the last years, a common base to evaluate these solutions and compare them with each other is missing. This paper presents a unified way to evaluate the performance of diferent re-keying algorithms running on the server side. A rekeying simulator estimates rekeying costs from a system point of view, which allows a reliable comparison between diferent rekeying algorithms. For this purpose, new system metrics related to rekeying performance are defined: the Rekeying Quality of Service (RQoS) and the Rekeying Access Control (RAC). By means of four simulation modes, these metrics are estimated by the simulator in relation to both the group size and its dynamics. A simulator prototype, implemented in Java, demonstrates the merit of this unified assessment method by means of a comprehensive case study.

Parallelization of operations is of utmost importance for efficient implementations of public key cryptography algorithms. Taking a clarification of parallelization methods at different abstraction levels of public key algorithms as a foundation, we propose a novel memory architecture for elliptic curve implementations with multiple modular multiplier units. This architecture is well-suited for different algorithms over GF(P) to be implemented on FPGAs. It allows the execution time to scale with the number of modular multipliers and features nearly no overhead compared to the mere runtime of the multipliers. The advantages of this distributed memory architecture is demonstrated by means of two different EC point multiplications algorithms

Hardware design is a process of refining an idea from a highly abstract form to a concrete, physical implementation. Along the way, a design is continually transformed from a given state of abstraction to another less abstract representation, finally ending with physical design. Such transformations are achieved through synthesis - a standard method in digital design. Analog circuits, however, are still designed in practice in a bottom-up, manual style. This paper summarises the results of past research in analog synthesis and outlines a refinement-centric methodology for analog circuit synthesis

This paper presents an automatic structure synthesis technique by partitioning the system representation, which consists of interconnected analog and mixed-signal behavioral models coded in VHDL-AMS. The proposed model code refining methodology restructures, refines, and simplifies behavioral models by means of code transformations of given abstract models. The fundamental approach for these transforms is code refactoring - an approach taken from software engineering and adjusted to the requirements of analog circuit synthesis. Through code refactoring one improves the comprehensibility, expandability, and reusability of a behavioral block model and restructures the model such that subsequent circuit synthesis steps may produce adequate structural representations of the intended behavior. Application examples demonstrate the feasibility of this approach to architecture synthesis.

The paper introduces dependability as an optimization criterion in the system-level design process of embedded systems. Given the pervasiveness of embedded systems, especially in the area of highly dependable and safety-critical systems, it is imperative to consider dependability in the system level design process directly. This naturally leads to a multi-objective optimization problem, as cost and time have to be considered too. The paper proposes a genetic algorithm to solve this multi-objective optimization problem and to determine a set of Pareto optimal design alternatives in a single optimization run. Based on these alternatives, the designer can choose his best solution, finding the desired tradeoff between cost, schedulability, and dependability.

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods

The proposed specification method denoted as hierarchical CoDesign Model allows a hierarchical system level specification of distributed embedded systems including both definition and reuse of IP cores. Input/Output Relations are introduced as a very general and powerful means of encapsulating internal implementation details and of describing data as well as control flow information on different levels of abstraction. Two novel algorithms are proposed, which allow deriving dynamically task descriptions for the IP encapsulation as well as flat specification models for design space exploration on different levels of detail. This reduces considerably the descriptive complexity of specifications and therewith the execution times of synthesis and design space exploration algorithms.

This paper presents a generalization of a previously proposed asynchronous wave-pipeline architecture. Four-phase and two-phase communication units supporting more than one wave in the logic are proposed. General feedback structures are then outlined. Simulations from a 16-bit add-and-shift ring demonstrate their feasibility. The same architecture is applicable for both datapath and control enabling the realization of complete high-throughput asynchronous systems.

Analog simulation methodologies for the generation of macromodels of analog functional blocks, as reported in literature, are of limited use in practical circuit simulation due to frequent accuracy and efficiency problems. In this paper, a new approach to model the behaviour of nonlinear functional blocks is proposed. The approach is based upon the principles of systems theory. The outlined methodology supports the mapping of models from component into behavioural level. The nonlinearity of complex analog modules is reflected efficiently while the electrical signals are maintained.

In this paper the synthesis of timed asynchronous circuits under the aspect of logic reduction is discussed. We introduce interval based timing constraints resulting from the system environment of such interface circuits into the well-known specification form of asynchronous circuits, called signal transition graphs (STGs). As a novel contribution we propose a method to synthesize the corresponding logic according to interface timing. In a first step, we present an efficient analysis algorithm for this timing model. Then a new synthesis procedure is proposed that exploits the results of the timing analysis in order to produce reduced logic implementations. Synthesis results of timed asynchronous circuit specifications demonstrate the advantages of this approach compared to other methods.

In this paper the introduction of interval based timing constraints in Signal Transition Graphs (STGs) is discussed. As a novel contribution we propose a general method to analyse these timing constraints according to different firing rules in cyclic STG. This method is based on the formulation and solution of an optimization problem. Results are presented for establishing the precedence relation of transitions, which is important in consideration of the synthesis process of asynchronous communication protocols.>