Time-dependent dielectric breakdown (TDDB) is a critical contributor to wear-out failures in semiconductors, aggravated by scaling of thin-oxide fabrication processes. Stress-induced leakage current (SILC) that increases with wear-out in these thin-oxide transistors correlates to TDDB hard failure risk, however existing in-field monitoring solutions struggle to characterize picoamp currents and maintain effective bias during measurements. We present a sensor for in-field predictive TDDB failure risk assessment of gate dielectrics based on SILC characterization via a current integration measurement scheme. The sensor enables constant voltage bias and current amplification during measurement within a simple 5-transistor topology. Our design is fabricated in a 12nm FinFET process and subjected to accelerated aging stress using an in-house test platform to verify the design, with eight sensor variants showing good correlation with simulation results. Observed SILC degradation and soft breakdown events allow for detailed analysis and comparison of transistor wear-out across gate oxide stack-ups, enabling future semiconductor in-field failure risk management strategies.

Ring oscillators are widely used for monitoring wear-out in semiconductor devices, providing a holistic view of degradation resulting from multiple mechanisms simultaneously affecting the inverter stages. In this work we present a ring oscillator sensor architecture for isolated monitoring of the contributions of bias temperature instability (BTI) and hot carrier injection (HCI) stress regimes in both NMOS and PMOS transistors. The design contributes a topology for HCI stress isolation, explicit consideration for degradation of auxiliary transistors, and enhanced comparative analysis capability through an interwoven oscillator layout technique. The sensor variants are implemented in a 12nm FinFET process then stressed and measured using a custom automated wear-out test system built using Rust. Our measurement results agree with simulations and illustrate the differences in degradation between stress regimes in non-planar transistors.

Wear-out reliability in integrated circuits is becoming an increasingly complex topic, with emerging high-reliability markets demanding stricter requirements, diverse workloads making stress characterization challenging, and sub-5nm device scaling aggravating variability in degradation processes. Efforts to tackle these complexities can benefit greatly from sophisticated techniques that effectively capture the variable and uncertain nature of semiconductor wear-out mechanisms. True-to-life stochastic modelling and computational Bayesian inference offer promising avenues in this pursuit but are difficult to leverage without a framework for specifying and evaluating wear-out models that capture this probabilistic information. We present a temporal wear-out simulator, Gerabaldi, as a foundation for enabling these statistical techniques for integrated circuit reliability engineering. The simulator introduces novel capabilities including layered stochastic parameter modelling, fully agnostic design enabling custom degradation model and stress test specifications, and wear-out model definition forms compatible with modern computational Bayesian inference frameworks. Here, we frame Gerabaldi within the context of existing wear-out analysis methods. We then present its key design features and two detailed example applications to illustrate the simulator’s capabilities.

Routing congestion is one of the many factors that need to be minimized during the physical design phase of large integrated circuits. In this article, we propose a novel congestion estimation method, called MEDUSA , that consists of three parts: (1) a feature extraction and “hyper-image” encoding; (2) a congestion estimation method using a fixed-resolution convolutional neural network model that takes a tile of this hyper-image as input and makes accurate congestion predictions for a small region of the circuit; and (3) a sliding-window method for repeatedly applying this convolutional neural network on a layout, thereby producing higher-resolution congestion maps for arbitrarily large circuits. The proposed congestion estimation approach works with both 2D (collapsed) and 3D global routing. Using both quantitative metrics and qualitative visual inspection, congestion maps produced with MEDUSA show better accuracy than prior estimation techniques. Global routers typically use estimation techniques during their first router iteration and then switch to using actual congestion information extracted from the intermediate router solutions. Experimental results within the same global router infrastructure show a significant impact on quality after the first routing iteration; other estimation techniques result in an average of 22% to 54% higher initial overflow counts. This initial quality improvement carries through to the final global routing solution, with other estimation techniques needing up to 5% more routing iterations and up to 3× more runtime, on average. Compared with other global routers, MEDUSA achieves comparable wire length results and lower total overflow counts (more legal global routing solutions) and is typically faster.

We introduce a methodology to predict degradation in an SoC device undergoing a thermally accelerated aging process. SoCs are usually stressed at high temperatures and voltages (above nominal) to accelerate their aging so that their reliability under nominal conditions can be predicted. Here we focus on the thermal acceleration process. We implement a ring oscillator-based test structure and consider its free-running frequency as our reference parameter to measure degradation. We analyze 500 hours of BTI-induced degradation behavior at different temperatures and observed that the final degradation can be confidently predicted from the measurements in first half of the experiment. This observation provides a new research avenue to predict reliability test results, such as HTOL, which lasts for 1000 hours and has a negative impact on the product’s time to market.

Dynamic Internet-of-Things (IoT) systems are nonlinear cyber-physical systems that move around and operate in the physical environment under the control of stability laws in the cyber world. An example of such systems are Unmanned Aerial Vehicles (UAV s), or drones. In this environment, fake nodes can masquerade themselves as real nodes, to fool the command and control functions that can target resource management and lead to Denial-of-Service (DoS) attacks. In this paper, we present a novel authentication framework to identify fake nodes from the real ones by deriving and monitoring the stability function. More specifically, we exploit the Lyapunov stability function to validate the authenticity of a drone's physical behavior. We use training traces from real nodes to derive the stability function, then use it to authenticate traces at runtime. Our technique is implemented in a tool called Phoenix. We evaluate Phoenix with a system simulator as well as a real-world drone. We find that Phoenix takes about 50 ms to distinguish fake from real nodes, achieves a recall rate of over 96% and a precision rate of 95%, and can foil even determined attackers with limited computational resources.

In the near future, Internet-of-Things (IoT) systems will be comprised of autonomous, highly interactive and moving objects that require frequent handshakes to exchange information in time intervals of seconds. Examples of such systems are drones and self-driving cars. In these scenarios, data integrity, confidentiality, and privacy protection are of critical importance. Further, updates need to be processed quickly and with low overheads due to the systems' resource-constrained nature. This paper proposes Dynamic Policy-based Access Control (DynPolAC) as a model for protecting information in such systems. We construct a new access control policy language that satisfies the properties of highly dynamic IoT environments. Our access control engine is comprised of a rule parser and a checker to process policies and update them at run-time with minimum service disruption. DynPolAC achieves more than 7x performance improvements when compared to previously proposed methods for authorization on resource-constrained IoT platforms, and achieves more than 3x faster response times overall.

Scan-based design-for-testability (DFT) structure is widely used to facilitate the testing of integrated circuits (ICs). However, it always incurs much test power consumption. In this paper, we propose an improved test power optimization method by inserting extra logic in scan chain. It explores suitable places in scan chain based on an accurate criterion to insert different linear functions so as to minimize the transitions caused by shifting test data through scan chain. We apply our method on different benchmark circuits and the experimental result shows that the proposed method is more efficient to reduce test power than other optimization methods by inserting extra logic while incurring low area.

With increasing design complexity, post-silicon validation has become a critical problem. In pre-silicon validation, coverage is the primary metric of validation effectiveness, but in post-silicon, the lack of observability makes coverage measurement problematic. On-chip coverage monitors are a possible solution, but prior research has shown that the overhead is prohibitive for anything beyond a small number of coverage points. This paper presents a novel solution for post-silicon coverage monitoring: fully instrument the design in emulation to sample the relationships between coverage points, and then use this statistical data to choose a small set of coverage points whose coverage provides high probability that all the other coverage points are covered as well; only that small set is instrumented on silicon. To demonstrate the method, we propose a simple feature selection algorithm based on Bayesian networks to choose the small set of coverage points. In experiments emulating a non-trivial SoC, our technique reduces the number of coverage monitors by 92%, yet predicts over 98% probability that all coverage points are covered.

Scan design is regarded as the best design-for-testability (DfT) discipline. High test data volume and long test time are always two major concerns that our work here addresses. Here we combine a test data compression technique and broadcast-based decompressor architecture to relieve these problems. We propose a new decompressor architecture with bidirectional shift register as a source chain to broadcast compressed data into parallel scan chains. It enables one more broadcasting mode which leads to a higher broadcast ratio. We also propose a heuristic method to order the scan cells in each sub scan chain to improve the broadcast ratio so as to reduce the test data and test time. We apply our method on several benchmark circuits and the experimental results show that our method can reduce test data volume by 22.8% and shorten test application time by 19.5% on average with low area overhead in comparison to other state-of-the-art approaches.

Effective techniques for post-silicon validation are required to better evaluate functional correctness of increasingly complex multi and many-core SoCs. However, there is little data evaluating the coverage of post-silicon validation efforts on industrial-scale designs. In this paper, we address this knowledge gap by instrumenting a nontrivial SoC with on-chip coverage monitors to measure the coverage achieved by typical post-silicon validation tests, such as booting the operating system (OS). We compare coverage achieved pre and post-silicon, and also measure the area overhead required to monitor post-silicon coverage. Our results show that the typical test of booting the OS often achieves high coverage, well correlated to what is achieved by pre-silicon directed tests, but in some blocks the coverage can be low or markedly different between pre and post-silicon, highlighting the importance of post-silicon validation in general and post-silicon coverage measurement in particular.

Current silicon test methods are highly effective at sensitizing and propagating most electrical faults. Unfortunately, with ever increasing chip complexity and shorter time-to-market windows, an increasing number of faults escape undetected. To address this problem, we propose a novel technique to help identify hard-to-find electrical faults that are not detected using conventional test methods, but manifest themselves as observable functional errors during functional test, system test, or during actual use in the field. These faults are too sequentially deep to be diagnosed using simulation, ATPG, or formal tools. Our technique relies on repeated full-speed chip runs that witness the functional bug, combined with some additional on-chip functional debug support and off-line analysis, to compute a possible set of suspected faults. The technique quickly prunes the suspect set, and for each suspect, it can provide a short test vector for further analysis. Experiments on the ITC'99 benchmarks demonstrate the effectiveness of our approach.

This work proposes design strategies applicable to self-test circuits for the functional validation of latches and flip-flops. The proposed methodology is also useful for, delay test and power consumption analysis that can also be performed over the circuits under test. Moreover, the evaluation of the impacts on circuit operation due to power supply variations and nanometer aging effects can be explored through the self-timed execution mode by monitoring the run frequency. The self-timed and self-checking characteristics make the proposed solutions very attractive for testing standard cell libraries as well as for comparing different implementations of such storage elements. We have validated the addressed strategies at transistor level through electrical simulations.

With the well-known trend of CMOS scaling as per Moore’s Law, traditional on-chip interconnect systems are reaching the point of having a very limited ability to meet the performance needs and specifications of Systems-on-Chip (SoCs). The conventional two-dimensional (2D) copper-based IC has inherent limitations due to the geometrical constraints of the planar structure. Innovative interconnect paradigms based on optical technologies, RF/wireless, carbon nanotubes, or 3D integration are promising alternatives that may indeed overcome the challenges encountered. In this paper we present an overview of different emerging non-traditional approaches to achieve massive degree of integration in a single chip. The advantages and underlying challenges of each method are highlighted.

Fault-tolerant design of network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction - these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, constrained with tight system performance specifications and other requirements In this paper, we provide a top-down view of fault-tolerance methods for NoC infrastructures, and present a range of metrics used for estimating their quality. We illustrate the use of these metrics by simulating a few simple but realistic fault-tolerant scenarios.

Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for networks on chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation.

A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant performance parameters - power, latency, and throughput. Experiments show that our approach is effective and requires minimal modifications of the existing design methods for NoC interconnects.

In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost

Design technologies for silicon-based integrated systems present unprecedented advantages and challenges, the former being related to the very high device density and the latter the increased presence of defects. In 45nm CMOS, in a single system on chip (SoC) over a thousand microprocessor cores, or modules of comparable complexity, may be integrated. On the other hand using System-in-Package (SiP) technology separate chips can be packaged together into a system with a very small form factor using a common 2D or 3D substrate. It is most suitable for the integration of heterogeneous technologies where single-chip integration is difficult or too expensive to pursue.

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a single-rectangle power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of zero power consumption for the detection of Data Retention Faults. This paper takes advantage of this zero power period and proposes a retention-aware test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarious in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the zero power period is fully utilized in a SoC environment.

The paper proposes a diagnosis scheme aimed at reducing the diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves on one proposed previously (Huang, D.C. et al., Proc. Int. Conf. VLSI Design, p.397-402, 2001; Huang and Jone, W.B., IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.21, no.4, p.449-65, 2002). The improvements are mainly twofold. On one hand, the diagnosis of time-consuming data retention faults (DRFs), which is neglected by the diagnosis architecture of Huang et al., is now considered and performed via a DFT technique referred to as the "no write recovery test mode" (NWRTM). On the other hand, a pair comprising a serial-to-parallel converter (SPC) and a parallel-to-serial converter (PSC) is utilized to replace the bidirectional serial interface, to avoid the problems of serial fault masking and defect rate dependent diagnosis. Results from our evaluations show that the proposed diagnosis scheme achieves an increased diagnosis coverage and reduces diagnosis time compared to those obtained by Huang et al., with negligible extra area cost.

Data-dependent jitter (DDJ) occurs when transmitting high-speed serial data signals through physical transmission medium. In test applications, the DDJ due to the test fixture and measurement equipment may be significant relative to the jitter under measurement. To avoid the loss of accuracy, special calibration methodologies are required to reduce the DDJ impact from test fixtures. This paper describes a novel technique for DDJ calibration for cases where signal pulse shape does not vary significantly from DUT to DUT. This method uses the signal history prior to each transition to estimate the test fixture induced DDJ and compensates for it regardless of data pattern or bit rate. We also introduce a new technique for separating the DDJ due to long-term history (in long transmission lines) from that of the short-term history preceding a transition

Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

Multi-Processor (MP-SoC) platforms are emerging as the latest trend in SoC design. Monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these high performance SoCs. Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature. By adopting a more structured network-based design paradigm, specific clock cycle requirements can easily be met. The precise focus of this paper is to show how the butterfly fat tree (BFT) can meet this objective when used as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.

Jitter can be decomposed into several subcomponents, each having specific sets of characteristics and root-causes. This work focuses on describing causes and measurement methods of jitter subcomponents. We first describe the relationship between a jitter PDF and bit error rate (BER) followed by a discussion on what causes jitter. Common jitter measurement methods are presented, along with an analysis of their respective advantages and disadvantages. Our recent research on the cause and practical measurement results and design issues of bounded uncorrelated jitter (BUJ), a subcomponent of jitter, due to crosstalk, is also presented.

Temperature is a physical magnitude that can be used as an observable quantity for IC testing purposes. The authors discuss in this paper the suitability of two temperature measuring strategies applicable to standard CMOS integrated circuits: a laser interferometer and a differential fully CMOS built-in temperature sensor.

Increasingly dense SRAMs of various bit capacities, embedded within current and future systems-on-a-chip (SoC) designs, command not only additional complexity due to required redundancy schemes, but also present serious challenges in regards to testing. In particular, the time needed for testing data retention faults (DRFs) and non-DRFs is growing rapidly. In this paper, we consider the overall production gain (OPG) and delay time associated with the testing of DRFs as the two selection factors for classifying embedded SRAMs, where OPG quantifies the trade-offs between yield and redundancy area overhead. These embedded SRAMs are categorized into four categories for testing non-DRFs and DRFs. Since both factors above are related to memory capacity, the four categories are named as very small, small, large, and very large types. According to this simple classification, we generate a set of four March test algorithms from an existing March SRD algorithm for each category respectively. As a comparison with March SRD, our investigations reveal that test time can generally be at least halved down to 22 nm technology for all capacity e-SRAMs with different IO numbers without losing defect coverage. The evaluation results also show that this reduction ratio is always no less than 50% for those with larger and larger and larger capacity predicted for future e-SRAMs in ITRS documents no matter what complex the comparison algorithms besides March SRD are.

A generic model for test architectures in the core-based system-on-chip (SoC) designs consists of source/sink, wrapper, and test access mechanism (TAM). Current test architectures for digital cores assume a direct connection between the core and the tester. In these architectures, the tester establishes a physical link between itself and the core, such that it can directly control the core's design-for-testability (DFT), such as the scan chains or primary inputs. This direct connection undermines the modularity in the generic test architecture by tightly coupling its elements. In this paper, we propose a network-oriented indirect and modular architecture (NIMA) for postfabrication test in an SoC design methodology. In NIMA, test stimuli and expected results for digital cores are first compiled into new formats and subsequently encapsulated into packets. These packets are augmented with control and address bits such that they can autonomously be transmitted to their destination through a switching fabric. Owing to the indirect nature of the connection, embedded autonomous blocks at each core are used to apply the test to the core and compare the test results with expected values. This indirect access to the core decouples test data processing at the core from its communication providing the basis for flexible and modular test design and programming. Moreover, NIMA facilitates remote-access of single or multiple testers to an SoC, and enables the sending of test data to an SoC in-field in order to test the chip in its target system. Finally, NIMA serves in contributing toward the development of new test architectures that benefit from network-centric SoCs. We present a first implementation of NIMA when applied to a number of SoC benchmarks.

This paper extends the model in (Wajih Dalai et al, Proc. of Int. Test Conf., p.518-523, 1999) to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixture impact. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (defects per million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.

Relying solely upon external ATE resources for scan test in complex SoC designs is increasingly difficult. In this work, we develop the concept and implementation of an embedded autonomous results analyzer (EARA) to be used in our modified dedicated autonomous scan-based testing (DAST) methodology. DAST introduces hierarchy and separates the functionality of ATE resources into two distinctive classes: a) test data communication; and b) test data control and observation. Consequently, test data control/observation functions are transferred to embedded blocks. In this work, we extend DAST to include the sending of expected test results along with the test stimulus to enable on-chip comparison. We present implementation results of EARA when applied to a number of SoC benchmarks.

The complexity of today's chips is such that relying solely upon external ATE resources is insufficient for scan test. In this work, we develop the concept of dedicated autonomous scan-based testing (DAST) by proposing a scheme that introduces hierarchy and separates the functionality of ATE resources into two distinctive classes: a) test data communication, and b) test data control and observation. To simplify the ATE for embedded digital core testing, we propose transferring ATE test data control/observation functions to one or more Embedded Autonomous Sequencers (EAS) dedicated to single or multiple embedded cores of an SoC We present implementation results of our DAST methodology when applied to a number of SoC benchmarks.

The continued market demand for GHz processors and high-capacity communication systems results in an increasing number of low-cost high volume ICs with multi-GHz clocks and/or multi-Gb/s serial communication interfaces. For such devices, timing specifications, e.g., jitter and skew, in the range of few picoseconds (RMS and/or p-p) are common. We describe an embedded core that allows such measurements. The core is small, functionally nonintrusive, and easily scalable for testing multiple circuits and signals on the chip. To reach the required sub picosecond accuracy, we present a novel measurement and data processing technique, based on noise scaling. The core has a standard low-speed serial interface.

Test access is a major problem for core-based system-on-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. One of the most important issues in designing a test access architecture is testing time. Here, several issues related to the design of an optimal test access architecture with the goal of minimizing testing time are discussed. These issues include the assignment of cores to test buses, the distribution of test data width between multiple test buses, and the estimation of test data requirements to satisfy an upper bound on the testing time. Previous works show that all of these problems are NP-complete. Here, we applied a genetic algorithm (GA) to solve these problems. Experiments were run on two hypothetical but non-trivial SOCs using the implemented GA. The results show a 40% improvement. The performance improvement is principally due to our removing the constraints of the necessity of serialization and allowing the system to handle serial or parallel test data loading for any core.

This paper focuses on the detectability of defects causing the gates of transistors in CMOS integrated circuits to float (open), i.e., on floating gate transistor (FGT) faults. Such faults are known to occur in practice. It is increasingly important to consider their detection to meet high quality requirements for circuits fabricated in deep submicrometer technologies. We focus on the detectability of FGT faults by the standard voltage- and current-based production test strategies that we refer to as static voltage (SV), dynamic voltage (DV), and static current (SC) test strategies. We demonstrate how the behavior of the devices caused by FGT faults depends on two classes of technological and topological parameters: the predictable and unpredictable parameters. We show that an FGT fault can induce abnormal logic values, additional delays, or increased power supply current. We introduce the concept of a detectability interval, i.e., the range of values an unpredictable parameter may assume that one allows for the fault detection using a specific test strategy. We illustrate how the detectability intervals for the SV and DV strategies complement that of the SC strategy. In addition, a new test scheme that results in an increased SC detectability of FGT faults is developed. Finally, we demonstrate the effects of initial trapped charges and the effects of coupling to surrounding metal on the detectability intervals of each of the test strategies.

This paper studies the Boolean (Static Voltage) and the I/sub ddq/ (Static Current) detection of Floating Gate faults due to large opens on transistor gate connections. We show that existing electrical models describing the behavior of FGT faults fail to allow the prediction of the floating gate potential due to the unpredictable parameters such as the initial changes and the polysilicon-to-bulk capacitance. We propose the twin-transistor structure as a basis for a general analysis of the Boolean and I/sub ddq/ detection of FGT faults. Using this analysis, optimal conditions for detection are defined for Boolean as well as I/sub ddq/ tests.

A novel built-in current integrator (BICI) is proposed for measuring the average supply current (I/sub DD/) of embedded circuit blocks. Such a circuit can be used both as a current signature generator and power monitor. The BICI uses only small capacitors (total 72 pF), a simple comparator, 7 switches, and a counter to perform integration over a long time (1 ms) window and digitize I/sub DD/. The BICI generates a digital signature proportional to I/sub DD/ and occupies a small area which make it suitable for BIST applications on mixed-signal ICs. The circuit has been implemented using a standard 0.5 /spl mu/ CMOS technology. Circuit performance trade-offs are analyzed and optimization guidelines provided. Simulation results are also included.

In this paper, a cost-effective DFT solution for the testing of ring oscillator-based VCOs is presented. The strategy is based on the reconfiguration concept: we propose to modify the circuit so that the VCO operates as a digital structure in test mode. The test can then be performed on a standard digital tester, avoiding the use of costly mixed-signal test equipment. In addition, simulation results show that the use of an adequate digital test strategy permits one to obtain better fault coverage than a classical functional center frequency test.

A new methodology for production phase testing of catastrophic short and open faults in Current Mode Logic (CML) circuits is proposed. The catastrophic faults induced in differential input CML circuits due to manufacturing defects are detected by manipulating the voltage levels of the inputs. The non-intrusive tests include functional (at-speed) tests, I/sub dd/ test, and a new test called common-mode test (CMT). Two high-speed interface circuits, a 622 Mbps SONET SIPO (Serial-in-Parallel-Out) and a PISO (Parallel-In-Serial-Out) are used as examples to illustrate the effectiveness of the tests. Using all three tests, SPICE simulations show that 88-90% fault coverage of catastrophic faults can be detected.

This paper studies the detectability of MOS floating gate transistor faults considering classical static voltage, dynamic voltage and static current strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the stable state making the circuit with a floating gate I/sub DDQ/ testable. It is shown that a combination of voltage and current testing can ensure 100% detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy.

The effectiveness of current testing for digital IC's has led researchers to explore the possibility of extending this concept to testing analog blocks of mixed-signal ICs. Unfortunately, test techniques developed for commonly-studied analog blocks such as op-amps and filters do not apply to non-linear blocks such as phase-locked loops. This paper focuses on investigating the effectiveness of using an operating power supply current monitoring technique to detect potential faults in a phase-locked loop (PLL) circuit.

We address test data compaction for built-in self-test (BIST). The thrust of the work focuses on BIST space compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as programmable space compactors (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set or test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area.

We examine the testing and fault simulation of an analog operational transconductance amplifier (OTA) biquadratic filter. Catastrophic as well as parametric deviation faults are considered. We determine if the simulated faults are detectable by comparing the output voltage from the fault-free case with each of the faulty cases. We also compare the fault coverage obtained with this voltage verification test versus the faults detectable with supply current monitoring tests. A simple bound is found for the detection of catastrophic faults in the presence of parametric variations. This bound is based on selecting the minimum comparator threshold for comparing the CUT output with the reference signal. As this threshold approaches the peak output deviation due solely to parametric variations, no additional catastrophic faults can be detected using the voltage checking and supply current tests.

Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computation of exact fault coverage, and shorter average test time. Conventionally, checking n signatures requires n references. Storing these references and comparing them with collected signatures imposes considerable hardware requirements. In this paper, we propose a novel multiple intermediate signature analysis scheme which checks n signatures against a single reference, thus making the circuitry for checking n signatures essentially the same as that for checking only one. The cost for implementing the proposed scheme is a very small nonrecurring CPU time expenditure in the design phase with no CUT modifications. In return, the proposed scheme yields significant recurring silicon area savings as well as reduced aliasing, and consequently higher test quality. This paper also defines a property for linear compactors that guarantees the existence of an initial state that necessarily yields two identical signatures at arbitrary check points for all circuits.>

Signature computation for linear compactors in a BIST environment is a computationally intensive process. In this paper, a fast compaction simulation algorithm is presented which uses superposition and look-up tables. While keeping memory requirements reasonable, this algorithm has a speedup advantage of at least one order of magnitude over traditional algorithms, and offers a threefold speedup over recently published "fast" algorithms. Our algorithm is also applicable to any linear compactor - while existing algorithms are restricted to only one type of compactor. Simulation results comparing the speed and memory requirements of the proposed compaction algorithm to that of existing compaction algorithms are given.>

Proposes a new BIST multiple intermediate signature analysis scheme which checks n signatures against a single reference. Therefore, the circuitry for checking n signatures is essentially the same as that for checking one signature. The scheme is based on a manipulation of the CUT's fault-free output sequence. No circuit modification is required. The cost for implementing the scheme is a small nonrecurring CPU time expenditure in the design phase. In return, the scheme yields significant recurring silicon area savings, and reduced aliasing.>

Many results regarding the probability of aliasing for multiple-input compactors have been derived under error assumptions that are not very realistic for VLSI circuits. Recently, the value of aliasing probability has been proven to tend to 2/sup -k/, where k is the number of binary memory elements of the linear compactor. This result is based on the assumption that the compactor is characterized by an irreducible polynomial and that the 'no error' vector has a probability different from zero. In these notes, the above result is generalized. More specifically, it is proved that it is valid if any two error vectors, neither of which needs to be the 'no error' vector, have probabilities of occurrence different from zero. To make the error model complete, the situation in which exactly one error vector has a probability different from zero is also considered. For the latter type of error distributions, the test lengths at which aliasing occurs are determined. Simple proofs for the results are provided; they are based on standard linear algebra notions and well-known theorems.>

Aliasing is studied for delay and stuck-open faults. It is shown that, as the test sequence length is increased, the probability of aliasing for such faults tend to 2/sup -k/, where k is the number of binary memory elements in a linear compactor. The result is based on the assumption that the linear compactor has an irreducible characteristic polynomial. Some recent results on combinational faults are special cases of the results presented here.>

Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure for path delay fault simulation whereby each node of the simulated circuit is evaluated only once per simulation pass in the backtrace process. Experiments with the ISCAS'85 benchmark circuits show that the procedure accelerates path delay fault simulation significantly. The proposed procedure can be implemented for parallel pattern path delay fault simulation. The concepts of SES and SESR can also improve both CPU time and memory efficiency of path delay fault simulation if only a subset of all the paths is considered.>

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR.>

The authors present a unified probabilistic model of count-based compaction that relates the probability of occurrence of the counted events to a circuit's fault detection probabilities. This model allows an identical treatment of all the different count-based techniques proposed to date, e.g. ones, transitions, edges, and spectral coefficients, by essentially reducing all techniques to simple ones-counting. From a Markov model of ones-counting, the authors derive asymptotic aliasing probabilities, and for finite test sequence lengths they developed a computation technique for determining the aliasing associated with the specifically mentioned schemes, as well as more general count-based compaction techniques, under various error models.>

Recent predictions about the aliasing behavior of linear feedback shift registers used in signature analysis with pseudorandom testing are validated experimentally. It is shown that the independent error model accurately predicts aliasing in these signature registers when test sets are selected at random. In practice, however, a circuit's test set is fixed, and it is shown that adopting a more general asymmetric error model, of which the independent is a special case, yields more accurate aliasing information, especially in the dynamic or non-steady-state region of the aliasing profile. The only additional information needed to apply the asymmetric model to signature analysis is the fault-free sequence. Since this sequence is needed in any case to compute the fault-free signature, the model can reflect test set ordering at no extra cost.>

The authors present a general technique for computing P/sub e/ for all possible shortened versions of cyclic codes generated by any given polynomial. The technique is recursive, i.e. computes P/sub e/ for a given code block length n from that of the code block length n-1. The proposed computation technique for determining P/sub e/ does not require knowledge of the code weight distributions. For a generator polynomial of degree r, and mod g mod nonzero coefficients, the technique yields P/sub e/ for all code block lengths up to length n in time complexity O(n mod g mod 2/sup r+ mod g mod /). Channels with variable bit error probabilities can be analyzed with the same complexity. This enables the performance of the code generator polynomials to be analyzed for burst errors.>

An algorithm, ALG-MK, for computing exact aliasing probabilities in signature analysis is derived from a Markov process model of signature analysis. A previous algorithm, ALG-BL, which was derived from a Boolean expressions formulation of the problem, is reformulated so that it can also be reviewed as being based on a Markov process. Both algorithms compute exact aliasing probabilities in signature analysis. The computational complexities of the two models are compared. It is shown that the time complexity of the iterative algorithm ALG-MK is O(L2/sup k/), disregarding slight possible start-up and termination improvements, while that of ALG-BL is O(Lf2/sup k+f/), where k is the size of the signature register, f is the number of feedback taps, and L is the test sequence length. ALG-BL requires more shift and add operations, but requires half the number of floating-point multiplications that ALG-MK requires. The space complexity of ALG-MK is O(2/sup k/), while that of ALG-BL is O(2/sup k+f/). It is also shown that ALG-MK and ALG-BL are formally related through a linear transformation of their state vectors. Both algorithms may be used to study aliasing under generalized error models.>

A unified probabilistic model of count-based compaction is presented that relates the probability of occurrence of the 'counted' events to a circuit's fault detection probabilities. This model enables an identical treatment to be made of all the different count-based techniques proposed to date, e.g., ones, transitions, edges, and spectral coefficients. Based on this model, the authors propose a computation technique for determining the error escape associated with these specific, as well as more general, count-based compaction techniques, under various error models.>

The authors propose a novel BIST (built-in self-test) scheme for ROMs that has an extremely low possibility of error escape. The scheme is referred to as exhaustive enhanced output data modification (EEODM). For the test generation. EEODM uses the exhaustive test technique. This guarantees the complete coverage of all combinational faults in the ROM. For output data compaction, EEODM uses an enhanced form of output data modification (ODM), along with bidirectional polynomial division. The hardware and test-time overhead was compared with that associated with other known BIST schemes. EEODM turns out to be very attractive, since it achieves much higher fault coverage than any of the other known schemes, and yet the associated overhead is very reasonable.>

An effort is made to validate experimentally predictions on aliasing in signature analysis registers under the independent error model. From the experimental results it appears that the independent error model accurately predicts the probability of aliasing in signature registers. The authors also provide justification for the adoption of a more general asymmetric error model of which the former is a special case; the latter can be used at no extra cost. Among the potential benefits in using the asymmetric error model is the subdivision of faults into classes based on pD and pDbar, the conditional probability, respectively, of the fault-free bit being 1 and the faulty bit being 0 and vice versa, whereby faults in a given class have the same probability of aliasing. Under the independent error model fault classification is based on a single parameter p. Use of an asymmetric model hence provides a better resolution in terms of the classification of faults based on aliasing probability. Experimental results also indicate that considering the asymmetric nature of circuit outputs yields more useful information, especially in the dynamic region of the aliasing curve.>

The authors present an analysis technique useful for studying the probabilistic behavior of signature analysis registers, which is in turn useful for studying the aliasing problem. The technique is applicable to all linear-feedback signature analysis registers, i.e. characterized by any linear-feedback polynomial, including multiple-input signature registers. The basis for the technique is the calculation of a sequence of probabilities where the ith element of the sequence corresponds to the probability that one particular stage of the linear-feedback signature register (LFSR) is in the state 0 or 1 after the ith bit has been shifted in the LFSR. The complexity for calculating such a single-stage state probability sequence is linear in time and space. The authors generalize such sequences to k-stage state probability sequences.>

A comparative study is presented of different methods of calculating multiple fault coverage and aliasing probability measures. The objectives are to describe the ways that these ratios are defined to give them a physical interpretation, and to separate the discussion of how to define the measure from how the measure might be actually obtained or calculated. The interpretation, accuracy, and applicability of the measures are discussed.>

Two automatic test pattern generation (ATPG) algorithms, PODEM and FAN, use heuristics that rely on testability measures (TMs). The use of random-pattern (probabilistic) TMs in these heuristics has already been proposed and investigated. The types of TMs proposed for such use are static. Static TMs (STMs) become increasingly unjustifiable as the search for a test pattern progresses. Dynamic TMs (DTMs) are introduced as a method to overcome the deficiency in the quality of STMs while still observing linear time and storage constraints. Based on results from several experiments, test-set generation strategy is devised that utilizes the advantages of both STMs and DTMs. From the experiments performed on benchmark circuits, compared to the strategy wherein only STMs are used to attain a given fault coverage, the proposed strategy requires considerably less CPU time to obtain a test set which attains the same fault coverage.>