This paper presents a method for automatic transcription of the diatonic Harmonica instrument. It estimates the multi-pitch activations through a spectrogram factorisation framework. This framework is based on Probabilistic Latent Component Analysis (PLCA) and uses a fixed 4-dimensional dictionary with spectral templates extracted from Harmonica's instrument timbre. Methods based on spectrogram factorisation may suffer from local-optima issues in the presence of harmonic overlap or considerable timbre variability. To alleviate this issue, we propose a set of harmonic constraints that are inherent to the Harmonica instrument note layout or are caused by specific diatonic Harmonica playing techniques. These constraints help to guide the factorisation process until convergence into meaningful multi-pitch activations is achieved. This work also builds a new audio dataset containing solo recordings of diatonic Harmonica excerpts and the respective multi-pitch annotations. We compare our proposed approach against multiple baseline techniques for automatic music transcription on this dataset and report the results based on frame-based F-measure statistics.

Placement is an important and challenging step in VLSI physical design. The placement solution can significantly impact timing and routability. In sub-nanometric technology nodes, several restrictions have been imposed on the placement solutions. These restrictions make designing an optimized and legal solution very hard. Achieving optimized placement solutions is especially challenging in regions with high-density utilization. The quality of placement solution can significantly impact the final circuit implementation. In this work, we present a cell spreading algorithm to move cells out from high-density utilization regions. Our algorithm opens up new spaces in regions with high cell concentration. These spaces can then be exploited by detailed placement algorithms to further optimize the placement solution. The objective of our technique is to reduce area density utilization while considering cell displacement and circuit delay. The outcome of the proposed algorithm is to obtain a uniform distribution of cells in the placement area while having minimal effects on the delay. To achieve this goal, our proposed algorithm uses branch and cut, and network flow techniques. Experimental results on industrial and academic circuits illustrate that our proposed algorithm can minimize circuit delay (up to 25%), cell displacement (up to 17μ m ), dynamic power consumption (up to 5.3%), and leakage power (up to 15%).

Due to the advanced stage of development on EDA science, it has been increasingly difficult to implement realistic software infrastructures in academia so that new problems and solutions are tested in a meaningful and consistent way. In this paper we present Rsyn, a free and open-source C++ framework for physical synthesis research and development comprising an elegant netlist data model, analysis tools (e.g. timing analysis, congestion), optimization methods (e.g. placement, sizing, buffering) and a graphical user interface. It is designed to be very modular and incrementally extensible. New components can be easily integrated making Rsyn increasingly valuable as a framework to leverage research in physical design. Standard and third party components can be mixed together via code or script language to create a comprehensive design flow, which can be used to better assess the quality of results of the research being conducted. The netlist data model uses the new features of C++11 providing a simple but efficient way to traverse and modify the netlist. Attributes can be seamlessly added to objects and a notification system alerts components about changes in the netlist. The flexibility of the netlist inspired the name Rsyn, which comes from the word resynthesis. Rsyn is created to allow researchers to focus on what is really important to their research spending less time on the infrastructure development. Allowing the sharing and reusability of common components is also one of the main contributions of the Rsyn framework. In this paper, the key concepts of Rsyn are presented. Examples of use are drawn, the important standard components (e.g. physical layer, timing) are detailed and some case studies based on recent Electronic Design Automation (EDA) contests are analyzed. Rsyn is available at http://rsyn.design.

As the interconnections dominate the circuit delay in nanometer technologies, placement plays a major role to achieve timing closure since it is a main step that defines the interconnection lengths. In initial stages of the physical design flow, the placement goal is to reduce the total wirelength, however total wirelength minimization only roughly addresses timing. A timing-driven placement incorporates timing information to remove or alleviate timing violations. In this work, we present an incremental timing-driven placement flow to further optimize timing violations via single-cell movements.For late violations, we developed techniques to reduce the load capacitance on critical nets and to obtain load capacitance balancing using drive strength. For early violations, we present techniques that rely on clock skew optimization, register swap and interconnection increase. Our flow is experimentally evaluated using the ICCAD 2015 Incremental Timing-Driven Contest infrastructure. Experimental results show that our flow can significantly reduce timing violations. On average, for long maximum displacement, the quality of results is improved by 67.8% with late WNS and TNS being improved by 2.31% and 10.84%, respectively, early WNS and TNS improved by 68.92% and 76.42%, respectively and congestion metric ABU improved by 74.9% compared to the 1st place in the contest. The impact on Steiner tree wirelength is less than 2.5%.

In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuit's timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential cells are replaced, seeking to minimize clock skew. After that, a quadratic formulation is used to further reduce critical path delays. An incremental legalization tool is also presented, which supports the methods developed in this work. Our Incremental Timing-Driven Placement flow can achieve, on average, 0.3%, 26.2%, 8.7% and 23.7% of the normalized quality score improvement compared to state-of-the-art algorithms.

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR) is an effective technique to handle complex constrained optimization problems and therefore has been successfully applied to solve the gate sizing problem. This article proposes an improved Lagrangian relaxation formulation for discrete gate sizing that relaxes timing, maximum gate input slew, and maximum gate output capacitance constraints. Based on such formulation, we propose a hybrid technique composed of three steps. First, a topological greedy heuristic solves the LR formulation. Such a heuristic is applied assuming a slightly increased target clock period (backoff factor) to better explore the solution space. Second, a delay recovery heuristic reestablishes the original target clock with small power overhead. Third, a power recovery heuristic explores the remaining slacks to further reduce power. Experiments on the ISPD 2012 Contest benchmarks show that our hybrid technique provides less leakage power than the state-of-the-art work for every circuit from the ISPD 2012 Contest infrastructure, achieving up to 24% less leakage. In addition, our technique achieves a much better compromise between leakage reduction and runtime, obtaining, on average, 9% less leakage power while running 8.8 times faster.

Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discreteness of the problem, along with complex timing models, stringent constraints and ever increasing circuit sizes make the problem very difficult to tackle. Lagrangian Relaxation is an effective technique to handle complex constrained optimization problems and therefore has been used for gate sizing. In this paper, we propose an improved Lagrangian Relaxation formulation for leakage power minimization that accounts for maximum gate input slew and maximum gate output capacitance in addition to the circuit timing constraints. We also present a fast topological greedy heuristic to solve the Lagrangian Relaxation Subproblem and a complementary procedure to fix the few remaining slew and capacitace violations. The experimental results, generated by using the ISPD 2012 Discrete Gate Sizing Contest infrastructure, show that our technique is able to optimize a circuit with up to 959K gates within only 51 minutes. Comparing to the ISPD Contest top three teams, our technique obtained on average 18.9%, 16.7% and 43.8% less leakage power, while being 38, 31 and 39 times faster.

This paper presents a flow composed by a set of heuristic algorithms to address the discrete gate sizing and Vt assignment problem for leakage power minimization while satisfying delay, load and slew constraints. The proposed flow combines the Fanout-of-4 empirical rule, the Logical Effort concept, a Simulated Annealing (SA) as the main engine, as well as a new set of specific optimization strategies to solve this difficult problem as formulated in the 2012 ISPD Gate Sizing Contest. The main contribution of this work is to show how a sequence of Simulated Annealing runs, starting from a solution given by Logical Effort, Fanout of-4 rule, and employing a set of new techniques can be used together to solve gate sizing problems of up to a million gates. New methods are presented to solve violations during the Annealing and a dynamic cost function is presented that helps SA to achieve different conflicting tasks during the optimization. The entire flow was able to achieve the second and first ranks in the ISPD 2012 Contest. A set of different experiments is presented to support design decisions and highlight the quality of the achieved results.

Despite the existence of several other alternatives for estimating delay of interconnects, the Elmore Delay Model still has been used for comparison of routing algorithms. The criterion used to establish Elmore's model as a confident metric for this purpose is the so-called Fidelity Property. In this work we investigate the Fidelity Property using nowadays interconnect parameters, in four routing scopes. For the first time the Fidelity is evaluated in actual algorithms comparison, one of the main utilities it was established for. What is found is that the original methodology used to evaluate this property hides a significant standard deviation. This standard deviation strongly impacts the capacity of Elmore's model to provide good certainty of choosing the best routing solutions among several ones. Additionally, the experiments of algorithms comparison show that different routing alternatives are appropriated for different routing scopes, with respect to metal layers, driver strengths and routing areas.

In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a maze router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.

This paper addresses the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. We present AMAZE, a fast maze router based algorithm that employs selected techniques to build optimized steiner trees. A biasing technique proposed for wire length improvement produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Our experimental results show that AMAZE is more effective to optimize delay to critical sinks than state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30%) while keeping the properties of a routing algorithm. We also analyzed the ability of AMAZE to handle blockages and verified experimentally that AMAZE produces tree with better delay to the critical sinks than P-Trees from 6% (5 pin nets) to 21% (9 pin nets). An important motivation for this work lies in the fact that, due to its acceptable run time and quality of results, AMAZE can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly.

This work explores an alternative model for area routing, which employs horizontally aligned terminals in each row of cells, providing channel-like routing areas. We have developed a two-layer router that decomposes the routing problem into smaller pieces and takes advantage of the low time complexity that channel routing has in order to provide fast and convergent area routing for channel-less cell-based circuits. Comparing to maze routing, our toll shows an average increase in wire-length of only 0.6%, and area increase of 7.2%, due to the insertion of spaces. But results show that it achieves 100% routing in almost linear time for our test circuits. This is the main contribution of this kind of simultaneous, variable-die approach when compared to traditional fixed-die methodologies. Convergence and short CPU times are crucial in many IC designs, mainly when time-to-market is a tighter constraint. But they can contribute also in any methodology helping to meet other design constraints by not getting stuck in non-convergent loops.

In this paper we discuss the migration of a 2D netlist with pre-placed I/Os to 3D circuits. For that, we present an algorithm to perform the partitioning of the I/O pins into various tiers targeting at I/O balancing and 3D-vias minimization. We formulate the netlist migration constrained with respect to the preservation of some original netlist properties. The I/O partitioning algorithm is based on the logic distance between I/Os. Since there is no literature on I/O partitioning for 3D circuits we compared our algorithm with two simplistic approaches that targeted balance and min-cut respectively. Experimental results show that our algorithm can reduce the number of 3D-vias compared to both algorithms, while balance is kept close to optimal. Most importantly, we showed that performing I/O partitioning separately we can reduce the number of 3D-vias even more than existing solutions in the literature for the netlist partitioning. Additionally, we studied the area impact of the 3D-vias resulted from the three algorithms targeting two different technologies for 3D circuits. We observed that especially in the bulk based technologies the 3D-via penalty is huge, favoring our algorithm

This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266 MHz, while the floating point unit reaches 235 MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.