Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Rajagopalan Jayakumar

dblp:j/RJayakumar · also R. Jayakumar · DBLP profile ↗
← Back
14ranked-venue papers
2as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 1 first-authorArtificial intelligence and machine learning · 5Applied, interdisciplinary, general and emerging computing · 2Graphics, computer vision, multimedia, augmented reality and games · 1Theory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 76% Hardware accelerators and domain-specific architectures · 19% Electronic design automation · 6%
Theoretical computer science
2 papers
Graph algorithms and graph theory · 100%
Artificial intelligence
1 paper
3D vision · 100%

Topics — the 11 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computer vision › 3D vision
shape matching
0.011992
Shapes Recognition Using the Straight Line Hough Transform: Theory and Generalization · IEEE Trans. Pattern Anal. Mach. Intell. 1992
Hardware reliability and fault tolerance › reconfiguration
array reconfiguration
0.011989
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays · IEEE Trans. Computers 1989
Hardware reliability and fault tolerance
fault-tolerant architecture
0.011989
Restructuring for Fault-Tolerant Systolic Arrays · IEEE Trans. Computers 1989
Hardware reliability and fault tolerance › fault-tolerant architecture
fault-tolerant VLSI array
0.011989
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays · IEEE Trans. Computers 1989
Hardware reliability and fault tolerance › redundancy
redundancy analysis
0.011989
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays · IEEE Trans. Computers 1989
Hardware accelerators and domain-specific architectures
systolic array
0.011989
Restructuring for Fault-Tolerant Systolic Arrays · IEEE Trans. Computers 1989
Graph algorithms and graph theory
graph algorithms
0.011989
O(n2) algorithms for graph planarization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Graph algorithms and graph theory › graph theory › graph transformation › graph modification
graph planarization
0.011989
O(n2) algorithms for graph planarization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Graph algorithms and graph theory › planar graphs
planarity testing
0.011989
O(n2) algorithms for graph planarization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation
hardware verification and test
0.011989
Restructuring for Fault-Tolerant Systolic Arrays · IEEE Trans. Computers 1989
Graph algorithms and graph theory › graph algorithms
network flow
0.011985
Comment on "Graph-theoretic proof of a network theorem and some consequences" · Proc. IEEE 1985

Methods — techniques the papers use, named apart from their topics

straight line hough transform · 0.01d correlation · 0.0retiming · 0.0programmable delays · 0.0lempel-even-cederbaum planarity testing · 0.0data-flow path derivation · 0.0RCS-cut · 0.0RC-cut · 0.0PQ-tree · 0.0
YearPublicationVenuePosition
2008 On designing a usable interactive system to support transplant nursing
A. Narasimhadevara, Thiruvengadam Radhakrishnan, B. Leung, Rajagopalan Jayakumar
J. Biomed. Informatics4
1993 A Systematic Approach for Designing Concurrent Error-Detecting Systolic Arrays Using Redundancy
Chang N. Zhang, Hon Fung Li, Rajagopalan Jayakumar
Parallel Comput.3
1993 A decomposable parameter space for the detection of ellipses
Derek Chi-Wai Pao, Hon Fung Li, Rajagopalan Jayakumar
Pattern Recognit. Lett.3
1992 Shapes Recognition Using the Straight Line Hough Transform: Theory and Generalization
abstract
A shape matching technique based on the straight line Hough transform (SLHT) is presented. In the theta - rho space, the transform can be expressed as the sum of the translation term and the intrinsic term. This formulation allows the translation, rotation, and intrinsic parameters of the curve to be easily decoupled. A shape signature, called the scalable translation invariant rotation-to-shifting (STIRS) signature, is obtained from the theta - rho space by computing the distances between pairs of points having the same theta value. This signature is invariant to translation and can be easily normalized, and rotation in the image space corresponds to circular shifting of the signature. Matching two signatures only amounts to computing a 1D correlation. The height and location of a peak (if it exists) indicate the similarity and orientation of the test object with respect to the reference object. The location of the test object is obtained, once the orientation is known, by an inverse transform (voting) from the theta - rho space to the x-y plane.>
Derek Chi-Wai Pao, Hon Fung Li, Rajagopalan Jayakumar
IEEE Trans. Pattern Anal. Mach. Intell.3
1990 Detecting parameteric curves using the straight line Hough transform
abstract
A novel approach for the detection of parametric curves using the straight-line Hough transform is presented. The transform function of a curve can be expressed as the sum of two terms, namely, the intrinsic term and the translation term. This representation allows a natural decomposition of the high-dimensional parameter space into three subspaces: the intrinsic curve parameters, translation, and rotation. By eliminating either the translation term or the intrinsic term, one can easily determine the parameters of the remaining term. The complexity of this method depends mainly on the angular resolution, which is relatively independent of the arc length of the curve. The computational complexity of this approach compares favorably with that of other approaches based on the Hough transform.>
Derek Chi-Wai Pao, Hon Fung Li, Rajagopalan Jayakumar
ICPR (1)3
1989 Parallel algorithms for recognizing handwritten characters using shape features
Hon Fung Li, Rajagopalan Jayakumar, M. Youssef
Pattern Recognit.2
1989 Improvements and systolic implementation of the hough transformation for straight line detection
Hon Fung Li, Derek Chi-Wai Pao, Rajagopalan Jayakumar
Pattern Recognit.3
1989 A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
abstract
Presents a critical study of two approaches, the classical RC-cut approach and H.T. Kung and M.S. Lam's (Proc. 1984 MIT Conf. Advanced Res. VLSI p.74-83, 1984) RCS-cut approach, for reconfiguring faulty systolic arrays. The amount of cell (processing element) redundancy needed to ensure successful reconfiguration into an n*n array is considered. It is shown that no polynomial bounded redundancy is sufficient for the classical approach, whereas O(n/sup 2/log n) redundancy is sufficient for the Kung and Lams approach. The number of faulty cells that can be tolerated in a given array regardless of their locations is characterized and derived. It is shown that, for both approaches, in almost all cases a square array has better fault tolerance than a rectangular array having the same number of cells. A minimal fault pattern in a 2n*2n array with 3n+1 faults that is not reconfigurable into an n*n array using either of the two approaches is established.>
Clement W. H. Lam, Hon Fung Li, Rajagopalan Jayakumar
IEEE Trans. Computers3
1989 Restructuring for Fault-Tolerant Systolic Arrays
abstract
The problem of restructuring systolic arrays with faulty cells is considered. An approach to derive the required data-flow paths and computational sites is proposed. The data skewing requirement, which must be satisfied to find an input schedule, is also discussed. Algorithms to restructure systolic arrays for three different architectures of processing elements are presented. A systematic method to retime the restructured array using additional programmable delays so that the retimed array satisfies the data skewing requirements is developed.>
Hon Fung Li, Rajagopalan Jayakumar, Clement W. H. Lam
IEEE Trans. Computers2
1989 O(n2) algorithms for graph planarization
abstract
The authors present two O(n/sup 2/) planarization algorithms, PLANARIZE and MAXIMAL-PLANARIZE. These algorithms are based on A. Lempel, S. Even, and I. Cederbaum's (1967) planarity testing algorithm and its implementation using PQ-trees. Algorithm PLANARIZE is for the construction of a spanning planar subgraph of an n-vertex nonplanar graph. The algorithm proceeds by embedding one vertex at a time and, at each step, adds the maximum number of edges possible without creating nonplanarity of the resultant graph. Given a biconnected spanning planar subgraph G/sub p/ of a nonplanar graph G, the MAXIMAL-PLANARIZE algorithm constructs a maximal planar subgraph of G which contains G/sub p/. This latter algorithm can also be used to planarize maximally a biconnected planar graph.>
Rajagopalan Jayakumar, Krishnaiyan Thulasiraman, M. N. S. Swamy 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1988 O(n²) Algorithms for Graph Planarization
Rajagopalan Jayakumar, Krishnaiyan Thulasiraman, M. N. S. Swamy 0001
WG1
1987 Dynamic Reconfiguration for Fault-Tolerant Systolic Arrays
Derek Chi-Wai Pao, Hon Fung Li, Rajagopalan Jayakumar
ICPP3
1986 Systolic Structures: A Notion and Characterization
Hon Fung Li, Rajagopalan Jayakumar
J. Parallel Distributed Comput.2
1985 Comment on "Graph-theoretic proof of a network theorem and some consequences"
Nirmal K. Bose, Krishnaiyan Thulasiraman, M. N. S. Swamy 0001, Rajagopalan Jayakumar
Proc. IEEE4