Resistive random access memory (RRAM)-based neuromorphic computing systems (RNCS) show great promise for low-power edge computing applications. However, hardware reliability issues in RRAM devices remain unresolved. Due to the inherent fault tolerance of RNCS, many faults do not immediately degrade system accuracy, but minor faults may pose latent risks. Meanwhile, traditional fault detection methods are insufficient for edge systems that require strict efficiency and real-time operation. This work proposes a data-driven approach based on multistage extreme gradient boosting (XGBoost) and adversarial-inspired test, specifically designed for fast online fault detection in RNCS, focusing on cell-level SAF detection under diverse fault distributions. Experiments on convolutional layers of pretrained convolutional neural network (CNN) models in RNCS demonstrate the framework’s effectiveness for real-time SAF diagnosis. Under low fault rate conditions, the proposed approach achieves an average recall of 99.8% and an average$F1$-score of 99.5%. In addition, the test dataset generated using the iterative fast gradient sign method (IFGSM) (adversarial-inspired test) effectively improves the distinguishability of RNCS fault-induced output signatures.

This paper presents an ultra-fine frequency offset synthesis (UFFOS) technique that achieves sub-parts-perbillion (sub-ppb, $\lt10^{-9}$) frequency resolution in FieldProgrammable Gate Array (FPGA)-based clock generation. To overcome the inherent limitation of conventional FPGA clocking techniques (e.g., PLLs/DLLs), where minimum frequency adjustments are restricted to the order of 1% ($10^{-3}$), UFFOS employs a novel architecture of cascaded phase interpolators (PIs) synchronized to a high-stability reference clock. This technique enables programmable sub-ppb frequency offsets through precise phase accumulation control. Implemented on an AMD Xilinx Virtex Ultrascale+ FPGA platform, UFFOS demonstrates frequency offsets ranging from $\mathbf{0. 9 ~ p p b}$ to 3.35 parts-per-million ($\mathbf{p p m}, \mathbf{1 0}^{\boldsymbol{-} \mathbf{6}}$). A comprehensive jitter decomposition analysis characterizes the synthesized clock’s time-domain performance. Furthermore, we propose a digital heterodyne frequency offset measurement (DHFOM) method capable of verifying sub-ppb-level frequency offsets with quantization errors on the order of parts-per-quadrillion (ppq, $10^{-15}$). Experimental validation confirms UFFOS as a robust solution for sub-ppb frequency offset generation, enabling applications demanding extreme frequency precision, including coherent optical communications, atomic clock synchronization, quantum computing control systems, distributed sensor networks, and next-generation softwaredefined radio architectures.

In modern high-speed communications systems, jitter tolerance testing becomes increasingly critical as signal rates continue to rise, playing a vital role in ensuring reliable data transmission and optimal system performance. As a core component of jitter tolerance testing, jitter injection must meet stringent precision and flexibility demands. This paper introduces a novel jitter injection module that integrates a programmable SiGe delay line (PDL) with an FPGA-based arbitrary signal generator, enabling flexible generation of diverse jitter profiles. The proposed solution enables cost-effective generation of Gaussian-distributed random jitter (RJ), sinusoidal/periodic jitter, and deterministic jitter (DJ) in unlimited combinations. Experimental results demonstrate injection of both periodic and random jitter components onto 28 GHz clock signals, with the module achieving ±7.4 femtosecond (fs) accuracy for random jitter and high flexibility in generating arbitrary profiles (e.g., sinusoidal jitter).

This paper presents an experimental comparison of multiplexing techniques for generating high-speed Non-Return-to-Zero (NRZ) test signals ranging from 28 to 64 Gbps using field-programmable gate arrays (FPGAs) and advanced SiGe components. Traditional high-speed signal synthesis methods, such as exclusive-OR (XOR) gates and multiplexers (MUXs), are evaluated for their performance in overcoming signal integrity challenges like jitter, edge-rate, and data-eye degradation. The study demonstrates that re-clocking input signals with high-speed flip-flops prior to XOR-based frequency doubling significantly reduces jitter, while DDR re-clocked 2:1 and 4:1 MUXs leverage dual-edge clocking to achieve higher data rates. Experimental results show that these techniques enhance signal quality, with metrics including total jitter (TJ) reduced to 7.88 ps and eye opening expanded to 77.84% at 28.125 Gbps. At 56.25 Gbps, the XOR gate alone yields a nearly closed eye opening of 1.39%, the combination of flip-flop and XOR gate improves it to 48.19%. The 2:1 MUX achieves the widest eye opening (53.31%). By exploiting the maximum operating rate of the 4:1 MUX, a 64 Gbps signal is achieved. This work highlights cost-effective, FPGA-based solutions for high-speed testing, addressing the critical need for affordable, scalable automated test equipment (ATE) required for next-generation integrated circuit validation.

This paper describes methods for reducing and measuring random jitter (RJ) of clock signals in multi-GHz test instruments. The methods are based on real-time averaging of parallel/synchronized signals with uncorrelated RJ. Prior work (up to 10 GHz) is extended by experimental demonstration up to 36 GHz with RJ below 200 femtoseconds (fs). The theory of operation is reviewed and experimental results are shown for 12 and 36 GHz. A de-embedding procedure is used to separate the jitter contribution of the test instruments (jitter "floor") from the measured values to obtain a better estimate of the actual ultra-low jitter values of the measured signals. The effects of amplitude imbalance, signal-skew, cycle-to-cycle jitter correlation, and component-added RJ are measured and analyzed.

This paper introduces a 4-stage jitter reduction circuit with 2 stages of frequency doubling to produce an ultra-low jitter, 54 GHz clock, synchronized to a 13.5 GHz ATE/BERT/FPGA reference signal. Jitter-reduction is achieved using 4 stages of real-time signal averaging, each with nominal reduction of 30%. The effects are cascaded to obtain ~3 times reduction in random jitter (RJ). The clock frequency is doubled twice to obtain a desired output frequency of 54 GHz, suitable for testing 54 Gigabaud and 108 Gigabaud devices (using double data rate, DDR clocking). Experimental results demonstrate reduction of random jitter below 200 femtoseconds.

This paper describes three methods for reducing random jitter (RJ) in Multi-GHz electronic test instruments. These are based on real-time averaging of periodic signals (clocks or reference signals). In each method, N multiple signals are phase-aligned and averaged to reduce jitter by (1/N)1/2. The first method uses multiple phase-locked sources and is evaluated at 1 GHz and 10 GHz. The second method uses integer-cycle delayed copies of a single source and has been shown effective at 4 GHz. A novel third method is introduced and characterized up to 10 GHz using multiple tuned delay line stubs. The three methods can be used individually or in various combinations as well as with traditional techniques (e.g., PLL-based methods). In one example, RJ~300 fs jitter is achieved using a single stage that combines two of the methods, starting with input RJSource~700 fs. Simulation of multiple-stage configurations suggest that “ultra-low” (100–200 fs) jitter may be feasible.

This paper introduces a scalable framework for the design of self-testable, self-correcting, and self-repairing digital systems. Modular redundancy and re-programmability are used to accomplish generic self-test and to enable self-repair. Bit error rates (BER) are measured throughout the design to distinguish between transient errors and errors due to semi- or permanent-logic faults. Tri-modular redundancy (TMR) is used for error correction and fault-isolation with a fourth module available for automated repair. Modular reconfiguration (repair) occurs automatically, so that the system continues to operate error-free even during partial dynamic reconfiguration (in FPGAs). The state of a repaired module is re-synchronized with the running system within one cycle after the damaged module is replaced. The framework is capable of simultaneous repair of multiple faults, while ensuring error-free operation. A case study evaluates the reliability improvement of an FPGA-based neural network image classification application.

This paper describes a low-cost extension module used to extend an FPGA-based development platform that enables digital testing up to 40Gbps. This platform typically operates up to 13.1Gbps and can be applied to test current main-stream I/O standards such as PCIE3.0 (8Gbps), USB3.1 (10Gbps) and Thunderbolt (10Gbps). The high bandwidth of an ultra-high-speed test module allows testing capability for future high-speed standards such as PCIE4.0 (32Gbps) and 40G Ethernet. An FPGA main board is built and programmed to control this plugin module for testing at across a wide range of data-rates. Using such "state of the art" FPGAs and careful design strategy of an economical FR4 plugin board, the data rate is extended to 40Gbps. This economical plugin module is implemented by multiplexing four high-speed channels from the FPGA into a single 40Gbps serial bit stream.

This paper describes a low-cost extension board used together with an FPGA-based test platform that enables digital testing up to 40Gbps. The high bandwidth of the board allows testing performance needed for future high-speed standards. An FPGA main board is built to control this plugin board for testing across a wide range of data-rates. The FPGA itself supports to transmit and receive signals up to 10Gbps. This economic plugin test module is used to multiplex four high-speed channels from the FPGA into a single 40Gbps serial bit stream.

This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost “host” test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel “pin electronics” (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and pre-emphasis, and a “shadow sampler.”

This paper proposes a new multi-channel testing architecture for high-speed eye-diagram. The proposed architecture reconstructs the eye-diagram of a multi-Gbps bit pattern with the combination of pin electronics and reconstruction algorithms. A scalability of the test system significantly increases in behalf of a monobit receiver and its designated reconstruction algorithm. A novel reconstruction algorithm using monobit receiver and subsampling clock enables the test system to monitor the signal quality in low-cost. The proposed architecture is implemented and demonstrated in a hardware prototype. Experiment with the hardware prototype shows that an eye-diagram of 3.2Gbps bit pattern can be reconstructed within sub-picosecond resolution by the proposed method with subsampling clock (below 100MHz).

In the recent past, there has been steady growth in the data transfer rate of modern digital serial communication systems. Consequently, accurate characterization of high-speed signal transmission lines is necessary for ensuring high signal integrity. Time domain reflectometry (TDR) has been widely used in prior research to characterize high speed interconnect. The accuracy of the characterization depends on the sampling rate and the slew rate of the TDR input excitation signal. At high speeds it is not always possible to deliver "perfect" (impulse/step) TDR stimulus. In this paper, an algorithm is presented to compensate for the inherent distortion in nonideal TDR stimulus to improve the accuracy of interconnect characterization. The algorithm is applied to the problem of micro strip transmission line characterization for identifying discontinuities in signal interconnect. Hardware measurements validate the effectiveness of the proposed technique.

Practical techniques for generating test signals between 10Gbps and 50Gbps are described. An historical review shows that the problem of extending ATE to higher rates has been around for several decades, with ever-increasing speed requirements. We demonstrate, in this paper that multiplexing techniques that permitted 40-50 Mbps testing in the 1980s (then using 10-20MHz ATE) can be applied to the present problem of achieved 1000x faster rates today (40-50Gbps). Some intervening steps are shown that achieved 5-10Gbps, and recently 12-24Gbps. These are extended to demonstrate synthesis of signals between 40 and 50Gbps. The paper is intended to aid others who might face similar challenges in testing high-end products prior to the day when 50Gbps ATE becomes common-place.

A multi-GHz arbitrary timing generator (ATG) design is described and demonstrated in a hardware prototype. The objective of the ATG is to realize ATE hardware that nearly matches the unlimited timing flexibility of software simulation tools. The ATG allows timing edges to be programmed at almost any desired point within the test, with minimal constraints. The delay of every edge can be changed on a cycle-to-cycle basis. The period (frequency) can be changed on a bit-by-bit basis. Real-time algorithmic calculation of timing values is accomplished using a pipelined FPGA controller so that highly complex timing sequences can be synthesized. The ATG generates timing edges according to the FPGA calculations, and combines these with serialized digital “pattern” data to create the desired signal waveforms. A prototype supports ∼10ps resolution and achieves approximately +/−20ps accuracy (including 6σ random jitter). Its maximum sustainable data rate is 3.2Gbps (non-multiplexed) and 6.4Gbps (multiplexed). Bursts patterns up to 10.0Gbps are also demonstrated. Minimum pulse-width is ∼70ps.

This paper describes the challenges associated with recovery of multi-GHz short burst communications in multi-channel systems, especially DWDM optical packet switching networks. Burst-mode data transmission complicates the standard methods typically used to recover embedded clock information and recover the serial data. Previously implemented solutions to this problem either constrain the test capability or are not extensible to higher signaling rates. A new approach, capable of locking in a single cycle at rates up to 10 Gbps is described in this paper. This solution applies to both the testing strategies and a receiver circuit used for an end-application optical switching network interface.

This paper describes and compares two methods for producing digital test signals up to 24 Gbps. Prototypes are experimentally characterized to determine signal quality, and the two methods are demonstrated and compared. The residual timing errors are dominated by jitter. Typical random jitter (RJ) is about 1.17ps to 1.4ps (RMS) including system measurement errors for the two methods. Deterministic Jitter (DJ) is between 2.4ps and 8.5ps. Total jitter (TJ) ranges between 18.9ps and 28.2ps at a bit-error-rate BER=10-12.

This paper presents a multi-function multi-GHz test module designed to enhance the performance capabilities of automatic test equipment (ATE). The test module is designed with a core logic block consisting of a high-performance FPGA. It also contains an application specific logic block that is designed to perform multiple functions not possible with the FPGA alone. We demonstrate five applications: high-speed signal multiplexing up to 16Gbps, loopback testing, jitter injection, amplitude adjustment, and timing adjustment. The loopback path allows testing up to 9.28Gbps. Digital timing adjustment up to 10ns in 10ps increments, and fine adjustment up to 61ps is shown. Jitter injection up to 81ps (p-p) and amplitude adjustment over a range of 600mV are demonstrated. The core logic block itself has capabilities to generate 10Gbps output signals with 38ps (p-p, BER = 2 × 10-5) jitter. The test module is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). A bypass option allows signals from the ATE to pass through to the DUT, permitting use of traditional ATE functions.

This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test module's functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ~32ps (p-p) jitter, while the loopback path adds ~20ps (p-p) jitter to the input signal.

Graphics processing is most often accomplished in standalone ASICs that were originally designed for gaming applications. The graphics processors produce visually appealing functionality based upon 3D rendering algorithms, but they can also require large amounts of power and typically have only short-term device availability. This paper proposes a novel architecture for graphics processing in an FPGA that is motivated by industrial applications that require low power, high reliability, low cost, and long-term device availability. Due to resource constraints and architectural constructs, many traditional graphics processing concepts do not translate well to FPGAs; hence, a graphics processing architecture crafted specifically for FPGAs is needed. The proposed architecture provides a high degree of scalability and flexibility to allow customization for unique applications, and it also features the migration of technology that previously has been used only for packet processing. The unique multi-threaded packet processing engine accelerates the line rasterization with a careful partitioning of the processing across software and hardware. The baseline architecture, which can be scaled for higher performance through parallelisms, will be capable of rasterizing over 50 million pixels per second -- more than enough for any application with XGA resolution. Future work will focus on the complete implementation and optimization of the architecture as well as an extension to support general-purpose computations (GPGPU) on the FPGA-based graphics processor.

An adaptable platform for the development of customized ATE and test-support modules is described. The purpose of the platform is to provide a hardware framework for assembling combinations of specialized test modules for applications that are not well addressed by conventional general-purpose ATE alone. The platform can also be used to test, characterize, and calibrate individual modules prior to use within either a platform-based application or within a traditional ATE environment. The paper describes some of the salient features of the platform and one completed example for an all-optical packet-switching network called ¿Data Vortex¿ operating at 2.5 Gbps on each of 18 channels (>40 Gbps aggregate burst data rate). Two other example modules demonstrate even higher data rates. One is a dual-channel, bidirectional 5 Gbps FPGA-based module with loopback, jitter-injection, and 2:1 XOR multiplexing (up to 10 Gbps). This module exploits recent advances in FPGA technology that enable very high data rates at relatively low cost. Another example module synthesizes two 10 Gbps data streams using 16:1 SiGe serializers; and then combines these using an InP XOR gate to form a 20 Gbps test stimulus channel. While the platform and modules have interesting characteristics, individually they do not form a complete solution. However the various possible combinations, together with special-purpose modules, may help solve some of the most difficult test applications in the near future. Therefore, this paper tries to present the key features in a way that the reader may extrapolate to future test challenges.

The ability to precisely control the timing of digital signals is especially important for multi-GHz testing applications where errors are measured in picoseconds or even 100fs. While many solutions exist for continuous clock-type signals, delay of wide-bandwidth data signals is not so easy. In this paper we introduce a novel technique for adjusting the delay of ~7 Gbps data signals on a picosecond scale without significant distortion. The approach is based on a timing/amplitude dependency effect observed in a variable-gain SiGe buffer. A prototype is demonstrated with a variable delay range of about 50 ps. This circuit is enhanced by adding a "coarse" delay section, including four 33 ps steps, to provide the desired total range of ~140 ps. The end application requires several of these circuits for deskewing parallel buses of 6.4 Gbps ATE signals. The circuit is also useful for injecting a variable amount of jitter, limited by the fine-delay adjustment range.

A 2-channel module for testing serial and parallel signals up to 12.8 Gbps is described. It is intended to extend the capabilities of an existing 6.4 Gbps ATE, serving as a plug-in module in an active device interface board (DIB). This prototype circuit provides (1) direct connections to ATE channels for DC parametrics and low-speed functional testing, (2) 2:1 multiplexing of 6.4 Gbps to produce 12.8 Gbps stimuli with picosecond deskew, jitter-injection, and amplitude adjustment, (3) 1:2 fanout of 12.8 Gbps DUT response signals to allow testing by two 6.4 Gbps ATE channels, (4) full-rate low-jitter active loopback path with amplitude adjustment, and (5) auxiliary outputs for parallel monitoring of both transmitted and received signals. The basic logical structure is presented, and features of the module construction are described. A novel high-bandwidth adjustable delay circuit is described, that is used for deskew and XOR-based multiplexing. The performance of the module is demonstrated between 5.0 Gbps and 12.8 Gbps.

Controlling jitter on a picosecond (or smaller) time scale has become one of the most difficult challenges for testing multi-gigahertz systems. In this paper we present a novel method for reducing jitter in timing-critical ATE signals. This method uses a real-time averaging approach to combine multiple ATE signals and produces timing references with significantly lower random jitter. For example, we demonstrate a 3times reduction in jitter by combining eight ATE signals (each with sigma=4ps) to produce a low-jitter signal (sigma=1.3ps). The measured jitter reduction is shown to closely match that predicted by theory. This counter-intuitive (but welcome) result is of general interest for the design of any low-jitter system, and is particularly helpful for multi-GHz ATE where precise timing is so critical

This paper presents the design and performance characteristics of a system designed to interface between a PCI Express port and an optical packet switched network as well as provide inline test capability for the whole system. A single lane of PCI Express traffic is inverse multiplexed across eight parallel channels and retransmitted in a burst packet at aggregate data rates of 20 to 36 Gbps. Testing options include loopback self-test, data synthesis and substitution in-line with or in place of system data, and variable channel-to-channel skew. The I/O interfaces also support a range of variable analog parameters such as peak output amplitude, output amplitude swing, and common mode ranges for the input and output to evaluate the performance of or adapt to changes in the opto-electronic components. This design flexibility also allows for use of the system in more conventional electronic applications with little or no required modifications.

This paper demonstrates the application of micro-electromechanical switches (MEMs) and SiGe logic devices for passive and active loopback testing of wide data buses at rates up to 6.4Gbps per signal. Target applications include HyperTransport, Fully-Buffered DIMM, and PCIexpress, among others. Recently-commercialized MEMs technology provides high bandwidth (>7GHz) in very small packages in order to support wide parallel buses. SiGe logic also supports >7 Gbps signals when active shaping of the waveform is required. Loopback modules are described with between 9 and 16 differential channels. Multiple cards handle very wide buses or multiple ports. Passive cards utilize MEMs for switching between the Loopback (self-test) mode and traditional ATE source/receiver channels (which are also used for DC parametric tests). It is this switching function that benefits from the MEMs increased density. Active loopback cards provide additional waveform-shaping functions, such as buffering, amplitude attenuation or modulation, deskew, delay adjustment, jitter injection, etc. The modular approach permits pre-calibration of the loopback electronics, and easy reconfiguration between design validation, characterization testing, and high-volume production testing.

The authors are developing alternative approaches for wafer-level packaging (WLP) of high-performance, high I/O-density chips. The electrical contacts are patterned onto the wafer surface using lithographic processes in order to provide high density I/Os at a very low cost per pin. In order to fully exploit these new packaging technologies, a compatible testing approach is also needed. This paper describes one of the WLP I/O structures, a new bare-die test socket, and a low-cost multi-GHz miniature tester. Our initial objective for this WLP technology is 5 Gbps; and the operation of interconnects, the bare-die test socket, and the miniature tester at this rate and slightly higher (6.4 Gbps), was demonstrated. The miniature tester alone is demonstrated up to 8 Gbps

This paper describes an economical approach to highspeed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices to be tested have built-in self-test features, thereby reducing the complexity of functional testing required. This also reduces the need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected to the top of a wafer probe card with multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-theshelf components. However its performance in some aspects exceeds that of traditional ATE. Measurements illustrate the tester generating programmable 5Gbps signals with a +25ps timing accuracy. The generated signals exhibit low jitter 50ps and have a rise time of about 120ps.

The paper describes two projects researching the development of new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about /spl plusmn/25 ps timing accuracy.

Existing digital automated test equipment (ATE) can provide signals at about 1 Gbps or slightly higher. To accommodate multi-GHz test needs, some ATE provide options for a few faster channels (up to 3.6 Gbps). However, leading-edge parts may require 100s of these signals and in some cases at even higher speeds (5 and 10 Gbps). This work describes a modular approach that allows for as many as 144 multiplexing and/or sampling channels to be added to existing ATE. The modules developed, so far include multiplexers, demultiplexers, and high-speed samplers that each support multiple high-speed differential signals. Production units operating up to 2.5 Gbps were introduced. We provide more detailed characterization of these modules and describe new modules targeting 3.2 Gbps and 5.0 Gbps applications. Various re-clocking techniques and proprietary calibration methods are used in order to reduce timing errors (especially jitter) to the sub-50ps range. The general system configuration, and key features of the newly developed modules are presented.

Abstract A multi-purpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core provides a substantial number of programmable I/O for testing circuits and systems. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. This technique has been expanded upon to produce greater functionality at higher frequencies. Based upon limitations of current ATE and BIST, the need for the digital test core is described. The test core concept is reviewed within an opto-electronic pattern generator and sampler with an eventual goal of terabit-per-second aggregate data rate. The performance of the device is discussed, and a second application of the digital test core is introduced as a nano-scale wafer-level embedded tester.

A system for testing multi-gigahertz digital devices is described that uses conventional automated test equipment (ATE), supplemented with multiplexing and sampling logic. The approach is similar to earlier work [I] that demonstrated feasibility. However, this current paper solves many of the practical problems that limited application in production environments. Specifically, embedded logic is used for fastheliable auto-calibration of critical timing signals to achieve improved accuracy (typically 225~s). Variable output-level buffers are included in the multiplexing logic to provide a range of input levels to the device under test. Coaxial relays selectively switch between high-speed and DC modes of testing. Air- and liquid-cooling is used to maintain the electronics temperature, and thereby stabilize time delays. The production version of the system is scalable up to 144 high speed differential pairs, each operating at 2.5 Gbps. Overall timing accuracy (OTA) is about +loops, and is typically much better. Timing errors are found to be dominated by the ATE timing uncertainty, which is nevertheless improved through the use of the embedded calibration logic [patent pending]. The OTA includes peakto-peak jitter (at a bit error rate of 10'l2). The system is demonstrated by applying it to an AMCC 17x17 cross point switch that supports data rates as high as 3.2 Gbps. Additional electronic modules are under development that will further extend the maximum data rate (initially to 3.2 Gbps, then to 5 Gbps and above), while tightening the OTA.

A general-purpose, reconfigurable logic circuit, including an FPGA and a standard USB communications port, is introduced to implement many of the functions of traditional automated test equipment (ATE). An optional port to local memory is included for applications requiring extensive test vector storage. The test core provides a substantial number of programmable I/Os for testing other circuits. It may be used either to enhance the capabilities of ATE or to provide autonomous testing within large systems or arrays of components. Based upon limitations of current BIST and ATE, the need for the digital test core is described. The test core concept is introduced, and a specific circuit design is presented. This design is first evaluated independently and is then embedded into two example applications, including: (1) a high speed transmitter/receiver, and (2) a continuity checker for high-density flip-chips.

There are several approaches that can be applied to the multi-Gigahertz testing problem. These can be classified as either (1) internal test, as in built-in self test (BIST), or (2) external test, as applied by automated test equipment (ATE). Both these general strategies are in widespread use today. Furthermore, they are often used together to solve particularly challenging test requirements. Since the BIST and ATE approaches each have their benefits and limitations, the combination of the two provides for a variety of trade-offs. However, another degree of freedom is represented by the introduction of active circuitry near to the DUT (typically mounted on the load board). This we refer to as a "test support processor" (TSP). Generally the approach may involve the use of BIST and ATE as well as the TSP itself.

The advent of terabit aggregate rate telecommunication devices and multi-gigahertz I/O interfaces is posing new challenges on the semiconductor and ATE industries. Telecom chipmakers are currently using ad hoc techniques to test these kinds of devices due to the lack of a credible commercial solution. This session highlights the challenges of testing multi-gigahertz interfaces and presents promising early solutions.

This paper describes a test application for an IC with over 200 logic signals each carrying multiple-gigahertz data. An aggregate data rate approaching a terabit-per-second is attained during the test. A high pin-count automated test system with a maximum frequency of 1.33 Gbps DNRZ is used as a development platform. Data rate tripling logic is added to the system to produce stimuli signals each with DNRZ rates up to 4 Gbps. High-speed sampling circuits are added to capture the device output signals at these same frequencies. Several example measurements illustrate the signal quality that is achieved. The extraordinary performance exhibited by this application represents one of the most challenging digital test applications reported to-date, and foreshadows expectations for future automated test equipment.

A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers has been described previously (1998). This method uses an active component located between the device-under-test (DUT) and the automated test equipment (ATE) to reduce electrical interconnect delays to less than 150 ps. In this paper, the transceiver array concept is extended to include higher-level test processes such as real-time algorithmic pattern generation (APG), multi-gigahertz signal multiplexing, and others. The active test component is therefore called a "Test Support Processor" (TSP). It greatly reduces the functionality and performance capability required of the ATE, while maintaining signal integrity, and improving overall test quality. In its minimum configuration, the TSP provides an array of technology-specific transceivers very close to the DUT. This reduces transmission line effects, allowing for at-speed test of fast I/O switching characteristics. This technique may lead to lower-cost. The TSP is specifically intended to complement and support existing DFT and BIST structures within the DUT. The use of the TSP provides an additional degree of freedom for partitioning the test problem, and may result in a significant paradigm shift for future ATE architectures. This paper describes variations of the TSP concept, its potential applications, and economic impact. Three variations are illustrated through prototype demonstrations, including: (A) a 2.67 Gbps test pattern source, (B) a transceiver array for testing a high speed 4 Mbit SRAM, and (C) a reconfigurable real-time APG for memory testing, implemented using a field-programmable gate array (FPGA).

A digital method has been introduced previously for testing the interconnections between signal pins within high-density substrates such as multichip modules. This technique, while very effective at detecting and diagnosing catastrophic faults (complete opens and low-resistance shorts), has limited sensitivity to "near" failures (resistive opens and high-resistance shorts). This paper quantifies the sensitivity of the original method for detecting several classes of near failures. The sensitivity is found to be on the order of 100 /spl Omega/ for both near opens and near shorts in a typical implementation. To improve upon this, a significant variation on the original method is introduced. Rather than rely entirely on resistance differences to produce detectable voltage variations, the new approach couples these with a fixed capacitance to produce an RC rise-time change. The fault is then diagnosed with greater precision while still using fixed-threshold comparators.

This paper addresses a critical issue faced in the testing of devices and modules that support bi-directional data paths switching in a nanosecond or less. Current methods are first summarized and clarified in order to highlight their limitations when applied to higher performance signals. Next, two alternatives are presented that overcome these limitations. An "interleaving" method uses a single, matched-impedance transmission line between the device-under-test (DUT) and the test system pin electronics. The transmission line delay is carefully matched to the desired data rate to avoid "bus contention" problems at the pin electronics receiver. This method supports high speed signals and switching rates, but is limited to discrete frequencies. The second method proposes the use of technology-specific transceivers, located very close to the DUT. This method greatly reduces the "transmission-line" effects and supports high speed bi-directional testing throughout a wide range of frequencies. Furthermore, it represents a significant paradigm shift from the traditional ATE architecture that has so far provided general-purpose pin electronics on every test channel. In the long run, separation and specialization of the "pin electronics" may ultimately reduce future ATE costs.

This paper describes a new high throughput test methodology for a new multi-chip module (MCM) substrate. This is based on a new MCM substrate technology which contains interconnects, embedded passive devices, and mixed-signal circuits, currently being developed by the Packaging Research Center at Georgia Tech. The resulting MCM modules are called SLIM (single layer integrated module). In this paper a best methodology for SLIM modules is discussed.

This paper describes the design and performance of low-cost electronics modules which can be used for testing multigigabit-per-second digital components and subsystems within an automated test environment. Pattern stimuli are generated at rates up to 2.67 Gbps with timing errors less than 50 ps. Pattern sensitivity is less than 40 ps and RMS jitter is typically about 8 ps. A high-speed differential buffer provides emitter-coupled logic (ECL) transitions in about 200 ps. A data-capture circuit is shown to sample repetitive waveforms with 2.67 Gbps data rates. It is estimated that the component cost per channel for a large ATE would be under $1000. Cost savings is achieved by eliminating unnecessary features, emphasizing simple yet precise design techniques, and use of commercially-available (low-cost) components.

This paper introduces a new approach for interconnect testing of unpopulated MCM substrates. Defect detection and diagnosis is performed using a variation of methods that have traditionally been applied using Boundary Scan registers. The new approach involves parallel application of digital signatures to all nets, while capturing the responses at every node. The responses of fault-free nets are identical to the applied signatures, while faulty nets exhibit corrupted signatures. Defect classification is accomplished by comparison of the faulty signatures, thereby isolating such fault mechanisms as: (1) shorts to ground, (2) shorts to power, (3) open nets, and (4) bridging shorts between nets. Current methods for unpopulated substrate testing utilize either resistive or capacitance probing techniques which rely on the use of moving probes. Therefore test times may be excessive for large area MCMs. The new approach is significantly faster due to the parallel nature of the test. Thousands of nets may be tested and diagnosed in a fraction of a second with this technique.

Discusses techniques for detecting and diagnosing interconnect faults in MCM substrates. The methods use stimuli to measure the attenuation and phase variations resulting from interconnect defects such as opens, shorts and high resistance connections. The processes are compared to alternative techniques and provide better resolution in resistance measurement.

Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. Hierarchical scene matching is a technique for reducing the amount of computation involved in scene matching applications. Most of the past research on this problem has concentrated on efficient software algorithms, and very little effort has been expended on custom hardware solutions. We describe the design of SMAC, a new VLSI architecture for Hierarchical Scene Matching. This architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining. The paper also describes the design and implementation of a prototype CMOS VLSI chip that implements the exhaustive search task of the scene matching algorithm.>

Summary form only given, as follows. The need for known good die for MCMs has been widely recognized. However, satisfying this need has presented many test challenges. Fortunately, the efforts of many workers are now providing the basic technology to assure the performance and reliability of die to be used in MCMs. Performance testing of ICs and chips on wafers is illustrated at gigahertz rates with improvements possible using membrane probes. The recent development of rapid thermal stressing for quick burn-in of ICs presents the possibility of avoiding chip carriers. The point of this paper is to emphasize the availability of effective test methods for known good die and to provide the reader with a solid reference base from which to choose the most appropriate method.>

Generation and measurement of gigahertz digital signals for testing ECL and GaAs ASICs has been demonstrated [I -101. However, achieving the high degree of accuracy needed for characterizing performance at these frequencies requires extreme attention to calibration issues. This paper describes some of the sources of timing error and the calibration techniques used to compensate for these. The techniques are demonstrated on an experimental Gigahertz digital tester. However, these methods are sufficiently general that they may be applied to other systems.

A system hus been described [I -61 for testing digital ECL or GaAs devices at rates above 1 Gbps. This system utilizes GaAs multiplexers for combining data ffom several (4 or 8) tester channels to form high speed data sources which are then used as DUT stimuli. Until recently, one of the main limitations of this approach has been the lack of comparable performance &multiplexers or, alternatively real time comparator electronics. In place of these, multi-pass testing can be used if the test system comparators have a high enough bandwrdth [7]. In ths paper, recent enhancements to the data generation electronics of the UHF test system are first reviewed. Next, designs are presented for high speed comparison circuits. These perform real-time comparison of DUT output patterns with expected data at rates above 500 Mbps.

The author describes high-speed digital circuits appropriate for use in testing devices at data rates above 1 Gb/s. A system which combines several test channels to form a smaller number of higher frequency data sources is described. Each combination of channels provides software-programmable data streams which are used as input stimuli to the device under test (DUT). The responses of DUT outputs are tested at high frequency through multipass monitoring of DUT outputs with existing comparators. Initial experiments have demonstrated the feasibility of this approach at rates above 1 Gb/s using digital GaAs logic. Burst rates above 2 Gb/s have also been achieved. The methods described are widely applicable to a variety of high-speed component technologies, including submicrometer CMOS, emitter-coupled logic, and GaAs.>