Potential advantages of analog- and mixed-signal nanoelectronic circuits, based on floating-gate devices with adjustable conductance, for neuromorphic computing had been realized long time ago. However, practical realizations of this approach suffered from using rudimentary floating-gate cells of relatively large area. Here, we report a prototype $28\times28$ binary-input, ten-output, three-layer neuromorphic network based on arrays of highly optimized embedded nonvolatile floating-gate cells, redesigned from a commercial 180-nm nor flash memory. All active blocks of the circuit, including 101 780 floating-gate cells, have a total area below 1 mm2. The network has shown a 94.7% classification fidelity on the common Modified National Institute of Standards and Technology benchmark, close to the 96.2% obtained in simulation. The classification of one pattern takes a sub-1- $\mu \text{s}$ time and a sub-20-nJ energy-both numbers much better than in the best reported digital implementations of the same task. Estimates show that a straightforward optimization of the hardware and its transfer to the already available 55-nm technology may increase this advantage to more than $10^{2}\times $ in speed and $10^{4}\times $ in energy efficiency.

This is a brief review of our recent work on memristor-based spiking neuromorphic networks. We first describe the recent experimental demonstration of several most biology-plausible spike-time-dependent plasticity (STDP) windows in integrated metal-oxide memristors and, for the first time, the observed self-adaptive STDP, which may be crucial for spiking neural network applications. We then discuss recent theoretical work in which an analytical, data-verified STDP model was used to simulate operation of a spiking classifier of spatial-temporal patterns, and the capacity-to-fidelity tradeoff and noise immunity o f spiking spatial-temporal associative memories with local and global recording was evaluated.

We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 μm2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The new memory cell arrays have been successfully tested, in particular confirming that each cell may be automatically tuned, with ~1% precision, to any desired subthreshold readout current value within an almost three-orders-of-magnitude dynamic range, even using an unoptimized tuning algorithm. Preliminary results for a four-quadrant vector-by-matrix multiplier, implemented with the modified memory array, gate-coupled with additional peripheral floating-gate transistors, show highly linear transfer characteristics over a broad range of input currents.

We have performed extensive numerical simulations of the autonomous evolution of memristive neuromorphic networks (CrossNets) with the recurrent InBar topology. The synaptic connections were assumed to have the quasi-Hebbian plasticity that may be naturally implemented using a stochastic multiplication technique. When somatic gain g exceeds its critical value g(t), the trivial fixed point of the system becomes unstable, and it enters a self-excitory transient process that eventually leads to a stable static state with equal magnitudes of all the action potentials x(j) and synaptic weights w(jk). However, even in the static state, the spatial distribution of the action potential signs and their correlation with the distribution of initial values x(j)(0) may be rather complicated because of the activation function's nonlinearity. We have quantified such correlation as a function of g, cell connectivity M, and plasticity rate η, for a random distribution of initial values of x(j) and w(jk), by numerical simulation of network dynamics, using a high-performance graphical processing unit system. Most interestingly, the autocorrelation function of action potentials is a nonmonotonic function of g because of a specific competition between self-excitation of the potentials and self-adaptation of synaptic weights.

In this letter, we have found a more general formulation of the REward Increment = Nonnegative Factor x Offset Reinforcement x Characteristic Eligibility (REINFORCE) learning principle first suggested by Williams. The new formulation has enabled us to apply the principle to global reinforcement learning in networks with various sources of randomness, and to suggest several simple local rules for such networks. Numerical simulations have shown that for simple classification and reinforcement learning tasks, at least one family of the new learning rules gives results comparable to those provided by the famous Rules A(r-i) and A(r-p) for the Boltzmann machines.

This report describes a preliminary evaluation of performance of a cell-FPGA-like architecture for future hybrid "CMOL" circuits. Such circuits will combine a semiconduc-tor-transistor (CMOS) stack and a two-level nanowire crossbar with molecular-scale two-terminal nanodevices (program-mable diodes) formed at each crosspoint. Our cell-based architecture is based on a uniform CMOL fabric of "tiles". Each tile consists of 12 four-transistor basic cells and one (four times larger) latch cell. Due to high density of nanodevices, which may be used for both logic and routing functions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semi-custom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance.

Hybrid semiconductor/nanodevice ("CMOL") technology may allow the implementation of digital and mixed-signal integrated circuits, including artificial neural networks ("CrossNets"), with unparalleled density and speed. However, previously suggested methods of CrossNet training may be impracticable for large-scale applications of these networks. In this work, we are describing two new methods of "in situ" training of CrossNets, based on either genuinely stochastic or pseudo-stochastic multiplication of analog signals, which may be readily implemented in CMOL circuits. The methods have been tested by numerical simulation of CrossNet-based perceptrons by error backpropagation on three problems of the Probenl benchmark dataset. The testing gave very encouraging results: CMOL CrossNets with their binary elementary synapses may provide, after the in situ training, classification performance at least on a par with the best results reported for software-based networks with continuous synaptic weights.

We have found a more general formulation of the REINFORCE learning principle which had been proposed by R. J. Williams for the case of artificial neural networks with stochastic cells ("Boltzmann machines"). This formulation has enabled us to apply the principle to global reinforcement learning in networks with deterministic neural cells but stochastic synapses, and to suggest two groups of new learning rules for such networks, including simple local rules. Numerical simulations have shown that at least for several popular benchmark problems one of the new learning rules may provide results on a par with the best known global reinforcement techniques.

Physics offers several active devices with nanometer-scale footprint, that can be best used in combination with a CMOS subsystem. Such hybrid circuits offer the potential for high defect tolerance combined with unparalleled performance. In this tutorial, we highlight key issues and architectural alternatives for this promising technology and outline the challenges posed by the hybrid circuits pose for design automation.

Hybrid “CMOL” integrated circuits, combining CMOS subsystem with nanowire crossbars and simple two-terminal nanodevices, promise to extend the exponential Moore-Law development of microelectronics into the sub-10-nm range. We are developing neuromorphic network (“CrossNet”) architectures for this future technology, in which neural cell bodies are implemented in CMOS, nanowires are used as axons and dendrites, while nanodevices (bistable latching switches) are used as elementary synapses. We have shown how CrossNets may be trained to perform pattern recovery and classification despite the limitations imposed by the CMOL hardware. Preliminary estimates have shown that CMOL CrossNets may be extremely dense (~107 cells per cm2) and operate approximately a million times faster than biological neural networks, at manageable power consumption. In Conclusion, we discuss in brief possible short-term and long-term applications of the emerging technology. 1 Introduction: CMOL Circuits Recent results [1, 2] indicate that the current VLSI paradigm based on CMOS technology can be hardly extended beyond the 10-nm frontier: in this range the sensitivity of parameters (most importantly, the gate voltage threshold) of silicon field-effect transistors to inevitable fabrication spreads grows exponentially. This sensitivity will probably send the fabrication facilities costs skyrocketing, and may lead to the end of Moore’s Law some time during the next decade. There is a growing consensus that the impending Moore’s Law crisis may be preempted by a radical paradigm shift from the purely CMOS technology to hybrid CMOS/nanodevice circuits, e.g., those of “CMOL” variety (Fig. 1). Such circuits (see, e.g., Ref. 3 for their recent review) would combine a level of advanced CMOS devices fabricated by the lithographic patterning, and two-layer nanowire crossbar formed, e.g., by nanoimprint, with nanowires connected by simple, similar, two-terminal nanodevices at each crosspoint. For such devices, molecular single-electron latching switches [4] are presently the leading candidates, in particular because they may be fabricated using the self-assembled monolayer (SAM) technique which already gave reproducible results for simpler molecular devices [5].

Our group is developing neuromorphic network architectures for future hybrid semiconductor/nanowire/molecular ("CMOL") circuits. Estimates show that such networks ("CrossNets") may eventually overcome the cerebral cortex in areal density, operating at much higher speed, at acceptable power consumption. In this report, we demonstrate that CrossNets based on simple (two-terminal) molecular devices can be configured to reproduce the behavior of any known neural network, either feedforward or recurrent, using a synaptic weight import procedure. Two other training methods including the global reinforcement (that may enable CrossNets to perform more intelligent tasks) are also described in brief.

Neuromorphic networks of high connectivity may be implemented using CMOS circuits as cell bodies, nanowires as axons and dendrites, and self-assembled single-molecule latching switches as synapses. The integration scale of such "CrossNet" circuits of acceptable size (/spl sim/30/spl times/30cm/sup 2/) may be comparable with that of the mammal's cerebral cortex (up to 10/sup 10/ neurons), despite the quasi-2D structure of the artificial networks. At the same time, the speed of information processing and network adaptation may be about 6 orders of magnitude higher than that of the brain, at high but manageable power consumption /spl sim/100 W/cm/sup 2/. We present an overview of the hardware implementation prospects, and possible strategies of CrossNet training. Two suggested Hopfield-mode training methods have been verified on numerical models of the networks. The results are consistent with our estimates of the maximum network capacity with an account for finite interconnect locality.

The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer of single electrons between small conducting "islands", have already enabled several important scientific experiments. Several other applications of analog single-election devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies.