Register windows are a processor feature that was originally developed to reduce the frequency for register spilling. This paper investigates how this mechanism can be used to implement a parallel shadow stack to protect return addresses from being corrupted. Furthermore, multiple improvements based on properties directly following the usage of register windows are proposed. Different configurations of parallel shadow stacks are evaluated based on prototype implementations on an ESP32 microcontroller and tested with different benchmarks. Performance overheads below 0.01% for CoreMark, below 3% for the worst case in MbedsTLS, and a worst case scenario of 22.153% for a recursive function show that our concepts are able to be efficiently developed even for embedded devices like the ESP32.

Honeypots serve as decoy systems that attract and monitor intruders, offering insights into their behavior. When interconnected, these honeypots form honeynets, simulating high-value environments to engage attackers and facilitate deeper analysis. However, in Industrial Internet of Things (IIoT) networks, deploying honeypots presents challenges such as static configurations, lack of network context, and difficulties in scaling.In this paper, we introduce TrapNet, a scalable, lightweight honeynet framework specifically designed for IIoT environments. TrapNet combines compact, on-site honeypots with large-scale, adaptive honeynets deployed on fog and cloud infrastructures using microservices. This approach enables fast deployment, scalability, and flexibility, providing an effective solution for IIoT cybersecurity. Our experimental results show that TrapNet efficiently detects intrusions while maintaining low resource overhead. Additionally, all code and configurations used in this study are publicly available, fostering further research and innovation in honeynet design and IIoT security.

5G networks are widely deployed in production lines to enhance automation in line with Industry 4.0, favored for their robustness and advanced security. However, they remain vulnerable to attacks such as jamming and zero-day exploits that can introduce alien traffic. The use of higher frequencies increases the likelihood of signal attenuation, degrading performance. When the network encounters these threats, performance declines, as reflected in 5G Key Performance Indicators (KPIs). In this work, we focus on a video conferencing use case that generates monotonous traffic under benign conditions, producing KPIs within an expected range. This serves as our data source, mimicking what may be a specific monotonous industrial operation and generating normal KPIs. Our goal is to design an autoencoder model to detect anomalous traffic, testing it against three types of anomalies: jamming, attenuation, and alien traffic. Additionally, we analyze how the characteristics of the three jamming types we designed affect detection capabilities. Using an over-the-air 5G testbed, we collect normal KPIs under benign conditions and anomalous KPIs under jamming and attenuation. We introduce alien traffic by running completely different use cases to generate further anomalous KPIs. The autoencoder model is trained on the normal dataset to detect KPI deviations caused by these attacks, flagging anomalous traffic. Our results indicate that alien traffic and attenuation are easily distinguishable from normal traffic, while jamming detection varies with attack severity. Barrage jamming, which affects the entire 5G spectrum, is the easiest to detect—achieving a 96.7% detection rate when the autoencoder uses the optimal threshold determined by Youden’s J statistic on the ROC curve.

This paper presents an approach to accelerate One-Class Support Vector Machines (SVM) using a hardware-friendly kernel that doesn't rely on multiplication operations, thus adaptable to hardware platforms. Leveraging Nyström approximation, we implemented a pipeline and compared its performance against a software implementation using libsvm. Furthermore, we evaluated the efficiency of our approach by deploying it on an FPGA. Our experiments, conducted on the SWaT dataset, demonstrate a 50x speedup using the FPGA implementation, achieving a classification time of 21 microseconds per instance. Importantly, we find no degradation in performance, as measured by the f-score of the attack class in the test set. This study explores the potential of hardware acceleration in optimizing anomaly detection systems for real-time applications.

In the ever-evolving landscape of Industrial Internet of Things (IIoT), security emerges as a critical concern. This paper delves into the realm of False Data Injection Attacks (FDIAs) within MQTT-based IIoT systems, specifically targeting the publisher-subscriber model. Our exploration unveils two distinct attack scenarios that exploit the vulnerabilities inherent in the communication fabric. In the first scenario, we demonstrate the potential chaos wrought by sending false data to subscribers, manipulating their perception and inducing actions that align with the attacker’s whims. The second scenario ventures into the heart of the publisher, where the attacker injects false data – deceptive status updates from other publishers e.g., Programmable Logic Controllers (PLCs). The repercussions ripple through the entire industrial process, impacting operations based on fraudulent information. This showcases the cascading effects of FDIAs, illustrating the profound threat they pose to the reliability and integrity of IIoT systems. For real-world attack scenarios, Our attacks were conducted on a small MQTT-based IIoT system, using the Fischertechnik Lernfabrik 4.0 9V factory. Finally, we proposes mitigation solutions to safeguard IIoT systems from the far-reaching consequences of false data manipulation. Our attack codes as well as a proof-of-concept are publicly available for further research.

Modbus is a widely-used industrial protocol in Supervisory Control and Data Acquisition (SCADA) systems for different purposes such as controlling remote devices, monitoring physical processes, data acquisition, etc. Unfortunately, such a protocol lacks security means i.e., authentication, integrity, and confidentiality. This has exposed industrial plants using the Modbus protocol and made them attractive to malicious adversaries who could perform various kinds of cyber-attacks causing significant consequences as Stuxnet showed. In this paper, we exploit the insecurity of the Modbus protocol and perform a stealthy false command injection scenario concealing our injection from the SCADA operator. Our attack approach is comprised of two main phases: 1) Pre-attack phase (offline) where an attacker sniffs, collects and stores sufficient valid request-response pairs in a database, 2) Attack phase (online) where the attacker performs false command injection and conceals his injection by replaying a valid response from his database upon each request sent from the HMI user. Such a scenario is quite severe and might cause disastrous damages in SCADA systems and critical infrastructures if it is successfully implemented by malicious adversaries. Finally, we suggest some appropriate mitigation solutions to prevent such a serious threat.

There are different ways to leverage Side Channel information into a successful attack against cryptographic hardware. The most constraint attack scenario assumes no knowledge about the internal states of the hardware during secret key processing and therefore provides no labels for power hungry deep learning algorithms, which are the state of the art in profiling attacks. In our non-profiled single-trace attack we used a statistical method the comparison to the mean to retrieve the initial key candidates and trained a highly regularized Support Vector Machine (SVM) using those candidates. We achieved an improvement in attack correctness of about 10%between the initial and final key candidates. We attacked two implementations of Elliptic Curve Scalar Multiplication. One is an ASIC produced in the IHP 250nm technology, where the hardware description was compiled using the compile_ultra option, which has been proven to increase the resistance against SCA attacks. Another one is an FPGA implementation, using the sequential addressing countermeasure, which minimizes the number of clock cycles with bus addressing leakage.

Real hardware PLCs are quite pricey, and some-times are unaffordable for scientists/engineers to build up small testbeds, and conduct their experiments or academic researches. For all that, the OpenPLC project introduces a reasonable alternative option and offers flexibility in programming codes, simulating physical processes and also the possibility of being utilized with low-cost devices e.g., Raspberry Pi and Arduino Uno. Unfortunately, the OpenPLC project was designed without any security in mind i.e., it lacks protection mechanisms such as encryption, authorization, anti-replay algorithms, etc. This allows attackers to fully access the OpenPLC and makes unauthorized changes e.g., start/stop the PLC, setting/updating passwords, removing/altering the user-program, and others. In this paper we conduct intensive investigations and disclose some vulnerabilities existing in the OpenPLC project, showing that an attacker without any prior knowledge neither to the user credentials, nor to the physical process; can access critical information and maliciously alter the user-program the OpenPLC executes. All our experiments were conducted on the latest version of the OpenPLC i.e., V3. Our experimental results proved that attackers can confuse the physical process controlled by the infected OpenPLC. Finally we suggest security recommendations for the OpenPLC founder and engineers to close the disclosed vulnerabilities and have more secure OpenPLC based environments.

S7 protocol defines an appropriate format for exchanging messages between SIMATIC S7 PLCs and their corresponding engineering software i.e., TIA Portal. Recently, Siemens has provided its newer PLC models and their proprietary S7 protocols with a very developed and sophisticated integrity check mechanism to protect them from various exploits e.g., replay attacks. This paper addresses exactly this point, and investigates the security of the most developed integrity check mechanism that the newest S7CommPlus protocol version implements. Our results showed that the latest S7 PLC models as well as their related protocols are still vulnerable. We found that adversaries can manipulate two hashes that play a significant role in generating keys and bytes for the encryption processes implemented in the S7CommPlus protocol. This allows to reproduce S7 packets and conduct several attacks that eventually impact the operation of the target PLC and the entire physical process it controls. To validate our findings, we test all the attack scenarios presented in this work on a cryptographically protected S7 PLC from the 1500 family which uses the S7CommPlusV3 protocol.

This paper presents Window Canaries, a novel approach to Stack Canaries for architectures with a register window that protects return addresses and stack pointers without the need of adding additional instruction to each potentially vulnerable function. Instead, placement and check of the canary word is moved to window exception handlers that are responsible to handle register window overflows and underflows. The approach offers low performance overhead while guaranteeing that return addresses are protected by stack buffer overflows without relying on a heuristic that decides which functions to instrument. The contributions of this paper are a complete implementation of the approach for the Xtensa LX architecture with register window option as well as a performance evaluation and discussion of advantages and drawbacks.

Control flow integrity (CFI) checks are used in desktop systems, in order to protect them from various forms of attacks, but they are rarely investigated for embedded systems, due to their introduced overhead. The contribution of this paper is an efficient software implementation of a CFI-check for ARM-and Xtensa processors. Moreover, we propose the combination of this CFI-check with another defense mechanism against return-oriented-programming (ROP). We show that by this combination the security is significantly improved. Moreover, it will also in-crease the safety of the system, since the combination can detect a failed ROP-attack and bring the system in a safe state, which is not possible when using each technique separately. We will also report on the introduced overhead in code size and run time.

Machine Learning (ML) and Artificial Intelligence (AI) depend on data sources to train, improve, and make predictions through their algorithms. With the digital revolution and current paradigms like the Internet of Things, this information is turning from static data to continuous data streams. However, most of the ML/AI frameworks used nowadays are not fully prepared for this revolution. In this paper, we propose Kafka-ML, a novel and open-source framework that enables the management of ML/AI pipelines through data streams. Kafka-ML provides an accessible and user-friendly Web user interface where users can easily define ML models, to then train, evaluate, and deploy them for inferences. Kafka-ML itself and the components it deploys are fully managed through containerization technologies, which ensure their portability, easy distribution, and other features such as fault-tolerance and high availability. Finally, a novel approach has been introduced to manage and reuse data streams, which may eliminate the need for data storage or file systems.

If devices are physically accessible optical fault injection attacks pose a great threat since the data processed as well as the operation flow can be manipulated. Successful physical attacks may lead not only to leakage of secret information such as cryptographic private keys, but can also cause economic damage especially if as a result of such a manipulation a critical infrastructure is successfully attacked. It can be expected that radiation-hard designs, specially crafted for space applications, are more robust not only against high-energy particles and short electromagnetic waves but also against optical fault injection attacks. In this work we investigated the sensitivity of radiation-hard JICG shift registers to optical fault injection attacks. In our experiments, we were able to trigger bit-set and bit-reset repeatedly changing the data stored in single JICG flip-flops despite their high-radiation fault tolerance.

In this paper, we discuss an approach which allows an attacker to modify the control logic program that runs in S7 PLCs in its high-level decompiled format. Our full attack-chain compromises the security measures of PLCs, retrieves the machine bytecode of the target device, and employs a decompiler to convert the stolen compiled bytecode (low-level) to its decompiled version (high-level) e.g. Ladder Diagram LAD. As the LAD code exposes the structure and semantics of the control logic, our attack also manipulates the LAD code based on the attacker’s understanding to the physical process causing abnormal behaviors of the system that we target. Finally, it converts the infected LAD code to its executable version i.e. machine bytecode that can run on the PLC using a compiler before pushing the malicious code back to the PLC. For a real scenario, we implemented our full attack-chain on a small industrial setting using real S7-300 PLCs, and built the database (for our decompiler and compiler) using 108 different control logic programs of varying complexity, ranging from simple programs consisting of a few instructions to more complex ones including multi functions, sub-functions and data blocks. We tested and evaluated the accuracy of our decompiler and compiler on 5 random programs written for real industrial applications. Our experimental results showed that an external adversary is able to infect S7 PLCs successfully. We eventually suggest some potential mitigation approaches to secure systems against such a threat.

Considering the recent transition towards renewable energy sources such as off-shore wind turbines, solar farms, and hydroelectric power plants, Structural Health Monitoring (SHM) of these novel infrastructures using Machine Learning (ML) methods has become extremely attractive. However, the strong dependence of energy-thirsty ML approaches on cloud computations limits their application at the edge, which is significantly important for SHM in remote locations. Therefore, development of edge-oriented machine learning models and their integration with edge-computing technologies such as neuromorphic platforms is vital for the real-time and on-site processing of sensory signals without cloud computations for SHM. Therefore, the objective of this work was to develop a neuromorphic-compatible ML model for time-series analysis of accelerometer data acquired from a wind turbine gearbox for fault detection purposes. The hardware-friendly model in this work provided an accuracy of 83.2% for the recognition of healthy and damaged gearboxes, providing promising results for off-cloud SHM using neuromorphic-computing technologies.

Abstract The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.

The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critical applications, extreme miniaturization of implementation technologies and intensive interaction with the physical world. These set tough requirements on mutually dependent extra-functional design aspects. The H2020 MSCAITN project RESCUE is focused on key challenges for reliability, security and quality, as well as related electronic design automation tools and methodologies. The objectives include both research advancements and cross-sectoral training of a new generation of interdisciplinary researchers. Notable interdisciplinary collaborative research results for the first halfperiod include novel approaches for test generation, soft-error and transient faults vulnerability analysis, cross-layer fault-tolerance and error-resilience, functional safety validation, reliability assessment and run-time management, HW security enhancement and initial implementation of these into holistic EDA tools.

In this paper we report on the results of selected horizontal SCA attacks against two open-source designs that implement hardware accelerators for elliptic curve cryptography. Both designs use the complete addition formula to make the point addition and point doubling operations indistinguishable. One of the designs uses in addition means to randomize the operation sequence as a countermeasure. We used the comparison to the mean and an automated SPA to attack both designs. Despite all these countermeasures, we were able to extract the keys processed with a correctness of 100%.

This paper shows how the Xtensa architecture can be attacked with Return-Oriented-Programming (ROP). The presented techniques include possibilities for both supported Application Binary Interfaces (ABIs). Especially for the windowed ABI a powerful mechanism is presented that not only allows to jump to gadgets but also to manipulate registers without relying on specific gadgets. This paper purely focuses on how the properties of the architecture itself can be exploited to chain gadgets and not on specific attacks or a gadget catalog.

Resistive Random Access Memory (RRAM) is a type of Non-Volatile Memory (NVM). In this paper we investigate the sensitivity of the TiN/Ti/Al:HfO2/TiN-based 1T-1R RRAM cells implemented in a 250 nm CMOS IHP technology to the laser irradiation in detail. Experimental results show the feasibility to influence the state of the cells under laser irradiation, i.e. successful optical Fault Injection. We focus on the selection of the parameters of the laser station and their influence on the success of optical Fault Injections.

Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper we investigate two different approaches to increase the inherent resistance of our hardware accelerator for the kP operation. The first approach aims at reducing the impact of the addressing in our design by realizing a regular schedule of the addressing. In the second approach, we investigated how the formula used to implement the multiplication of GF(2n)-elements influences the results of horizontal DPA attacks against a Montgomery kP-implementation. We implemented 5 designs with different partial multipliers, i.e. based on different multiplication formulae. We used two different technologies, i.e. a 130 and a 250 nm technology, to simulate power traces for our analysis. We show that the implemented multiplication formula influences the success of horizontal attacks significantly. The combination of these two approaches leads to the most resistant design. For the 250 nm technology only 2 key candidates could be revealed with a correctness of about 70% which is a huge improvement given the fact that for the original design 7 key candidates achieved a correctness of more than 90%. For our 130 nm technology no key candidate was revealed with a correctness of more than 60%.

This paper reports an algorithm for the detection of three elementary upper limb movements, i.e., reach and retrieve, bend the arm at the elbow and rotation of the arm about the long axis. We employ two MARG sensors, attached at the elbow and wrist, from which the kinematic properties (joint angles, position) of the upper arm and forearm are calculated through data fusion using a quaternion-based gradient-descent method and a two-link model of the upper limb. By studying the kinematic patterns of the three movements on a small dataset, we derive discriminative features that are indicative of each movement; these are then used to formulate the proposed detection algorithm. Our novel approach of employing the joint angles and position to discriminate the three fundamental movements was evaluated in a series of experiments with 22 volunteers who participated in the study: 18 healthy subjects and four stroke survivors. In a controlled experiment, each volunteer was instructed to perform each movement a number of times. This was complimented by a seminaturalistic experiment where the volunteers performed the same movements as subtasks of an activity that emulated the preparation of a cup of tea. In the stroke survivors group, the overall detection accuracy for all three movements was 93.75% and 83.00%, for the controlled and seminaturalistic experiment, respectively. The performance was higher in the healthy group where 96.85% of the tasks in the controlled experiment and 89.69% in the seminaturalistic were detected correctly. Finally, the detection ratio remains close ( ±6%) to the average value, for different task durations further attesting to the algorithms robustness.

Side channel attacks take advantage from the fact that the behavior of crypto implementations can be observed and provides hints that allow revealing keys. In this paper we present a novel approach to prevent SCA or at least to increase the effort to reveal keys significantly. Our approach is based on the fact that there are some functions used in cryptographic operations that can be implemented using different formulae or algorithms. These algorithms come with their individual complexity that results in individual circuits with individual power consumption. So, if the crypto implementation uses these different algorithms whenever it is executed or if the sequence in which the different algorithms are used is randomized, extracting the key gets extremely challenging if not impossible. Applying our idea is extremely challenging when it comes to ASIC implementations. The point here is that the functionality is fixed and cannot be altered after production. But we discuss that a runtime permutation of the relation between operands and algorithms used for their processing that alters the observable behavior in the same way as executing different algorithms.

In this paper, we describe a new non-volatile memory, based on metal-insulator-metal that provides performance benefits compared to standard Flash memory. In addition and more importantly, it comes with some advantages with respect to side channel attacks, i.e., its structure prevents by default optical analysis.

Sensor nodes compensate clock drift with guard times (GT), which results in idle listening. By applying prediction methods nodes can limit drift uncertainty for upcoming frames and shorten GT. However, a common solution based on linear regression requires floating-point arithmetic, i.e. large computation and memory overhead. We present an approach for drift prediction based on moving average, which works well with basic mathematical operations. It achieves similar accuracy to linear regression in indoor environments (the standard deviation of the drift prediction is less than a clock tick for 1-minute period) and even better results on some nodes outdoors. Moreover, it needs only 3 previous drift samples for accurate drift estimations. Our two-week drift experiments revealed that in outdoor scenarios nodes received 99% of frames with GT 8× shorter than the worst case. We exploit the idea of deliberately giving up the reception of approx. 1% of frames in order to use very short GT and to reduce idle listening. After applying our drift prediction approach we shortened GT by 95%. It results in 10% lifetime gain for IEEE 802.15.4.

This paper introduces a technology convergence adaptor for a previously presented Inter-MAC architecture for heterogeneous home area networks. Its main task is to translate technology-dependent link metrics into a machine readable common language. This language allows for the description of various service and application classes and provides means to describe link metrics of underlying MAC protocols. Based on this description technology-dependent conversion formulae can be integrated, which enable the calculation of technology-independent quality of service metrics. These metrics are essential for path selection and admission control in heterogeneous meshed home area networks. Example conversion formulae for wireless LAN based on IEEE 802.11 [2] are given, which can be well described in the proposed common language.

Wireless communication and smart sensors and actuators pose means to sustainably improve automation technology. Unfortunately they also cause an abundance of new challenges regarding security and safety of the system. After introducing the security concepts, this paper discusses an engineering methodology to cope with security requirements in context of industrial automation. Two practical examples demonstrate how the solutions even for pretty similar scenarios can differ significantly. The proposed development flow promises a reliable objective engineering of proper system solutions. Key concepts of the flow are a holistic goal description and an iterative composition algorithm that inherently applies and extends existing knowledge.

Realizing highly reliable wireless sensor networks with a long lifetime is a challenging task. A long lifetime is normally achieved by low duty cycles and rare activity. High reliability requires the replication of data to cope with dying nodes, network fragmentation, etc. These problems become even harder to tackle in networks with no wired sink (decentralized networks), which can synchronize the nodes and store data. We thoroughly investigated the challenges and present a reasonable approach, which adopts cross-layer rendezvous and data dissemination schemes. Our protocol can achieve very good results for lifetime, efficient replication handling and data gathering in decentralized sensor networks. Off-the-shelf sensor nodes based on our approach offer a lifetime of two years. However, our simulation results reveal that very long sleep phases may lead to increased power consumption, which is not expected.

Wireless sensor networks (WSN) are considered to be the key-enabler for low cost highly distributed applications in the area of homeland security, healthcare, environmental monitoring etc. A necessary prerequisite is reliable and efficient event detection. This paper introduces a novel approach for

The home network of the near future will be a heterogeneous broadband network supporting the use of wired as well as wireless transmission technologies. The variety of services will range from HDTV via gaming to emergency services in the telemedicine area. In this paper, we introduce a technology-independent protocol layer called Inter-MAC which provides a common infrastructure to all home networking devices. The Inter-MAC can establish a connection via different transmission technologies while ensuring appropriate QoS. Key to this is the capability to correctly interpret technology-dependent PHY and MAC parameters for determining QoS when selecting initial and alternative paths, as well as the feature of admission control. Our simulations indicate clearly that the Inter-MAC approach can cope with varying loads, for instance, the time the jitter needed to stabilize was as short as 4 s. The reduced QoS was not noticeable by the user since the jitter introduced by handling additional HDTV flows was less than 0.2 ms for the existing and less than 0.7 ms for the new flow.

This paper shows how complex security-related design decisions in wireless sensor networks can be made less difficult with a proposed supporting tool. As case study in this paper we focus on in-network-aggregation which is a promising option to reduce network effort. We introduce several algorithms for concealed data aggregation, each with its own benefits and drawbacks concerning security issues but also with respect to code size, processing overhead etc. Selecting the optimal combination requires in-depth knowledge of programming resource constrained devices, protocols for those devices, and last but not least significant background in security. Our proposed configuration tool - named configKIT - has been designed to cope with such complexity. This paper presents how configKIT works, how it will be set up, and how it can be applied in practice. The pre-compiler assessment process considers memory, energy and security parameters and provides reliable application-dependent configurations to the developer before a single line of code is written. The approach can reduce development time significantly and enables even complex and sophisticated security algorithms to a broader public.

Sensor Networks are envisioned to be used in large variety of applications - health care, homeland security etc. - which require high reliability. Due to the fact that the sensors need to be low cost they have only scarce resources leading to a certain level of failures of sensor nodes or sensing devices attached to the nodes. For the applications mentioned reliable and fault tolerant sensor networks are in great demand. Available fault tolerant solutions are mainly customized approaches that revealed several shortcomings. We present an event specification language that allows configuring the level of reliability of a certain sensor network. It explicitly regards heterogeneous sensing capabilities and allows defining complex events as well as tailor made voting schemes. Features for multi-event detection facets and for fine-grained event-related fault tolerance are also part of the language. Our approach significantly enhances service and maintenance features and enables online configuration of sensor networks.

editorial Free Access Share on Guest editorial: Service-oriented computing Authors: Qusay H. Mahmoud University of Guelph, Canada University of Guelph, CanadaView Profile , Peter Langendoerfer IHP, Germany IHP, GermanyView Profile Authors Info & Claims ACM Transactions on Internet TechnologyVolume 8Issue 3May 2008 Article No.: 11pp 1–3https://doi.org/10.1145/1361186.1361187Published:28 May 2008Publication History 0citation526DownloadsMetricsTotal Citations0Total Downloads526Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this paper we discuss algorithms that allow the concealed data aggregation (CDA) in wireless sensor networks. We describe and evaluate three algorithms that were reported to suit to the WSN scenario. As result of the evaluation, where we emphasize the awareness to potential attack scenarios, we present a brief overview of strengths and weaknesses of the algorithms. Since no algorithm provides all desirable goals, we propose two approaches to cope with the problems. The first is the successive combination of two algorithms. It increases security, while the additional efforts can be minimized by carefully selected parameters. For the second approach we face specific weaknesses and engineer mechanisms that solve the particular issues. With the considered homomorphic message authentication code and a discussion of the id-issue we exemplary evaluate the two biggest issues of the very promising CMT algorithm.

Privacy in the Internet is currently not addressed or just stated to tacit acceptance. The user is left to either accept or deny the contractual conditions. A negotiation and thus dynamic contract placement would allow for fairer chances concerning privacy. This article introduces a data-model to describe negotiation preferences and the resulting contracts. It is described, how proposals of contracts are to be compared with the preferences for acceptance and what steps of negotiation can be taken. This model is examined for privacy contracts between enterprises and their customers.

Securing communication channels is especially needed in wireless environments, but applying cipher mechanisms in software is limited by the calculation and energy resources of mobile devices. If hardware is applied to realize cryptographic operations, cost becomes an issue. We describe an approach which tackles all three of these points. We implemented a hardware accelerator for polynomial multiplication in extended Galois fields (GF) applying Karatsuba's method iteratively. With this approach, the area required is reduced to 2.1 mm/sup 2/ in comparison to 6.2 mm/sup 2/ for the standard application of Karatsuba's method, i.e., for its recursive application. Our approach also reduces the energy consumption to 60 per cent of the original approach. The price we have to pay for this achievement is an increased execution time. In our implementation, a polynomial multiplication takes 3 clock cycles, whereas the recursive Karatsuba approach needs only one clock cycle. However, considering area, energy and calculation speed, we are convinced that the benefits of our approach outweigh its drawback.

In this paper we present a new approach for the automated mapping of formal descriptions into activity thread implementations. The approach resolves semantic conflicts by reordering of statements at compile time. This simplifies the mapping process and considerably improves the efficiency of the generated code. The approach is implemented in the SDL compiler COCOS. We describe the approach as well as its implementation and prove how semantic conflicts are resolved. Finally we present measurements which show the achieved performance gain.