This live demonstration relates to our paper titled "Smart Watchdog Mechanism for Fault Detection in RISC-V" also published at ISCAS 2025. Spiking neural networks (SNNs) can realise low power and area implementations compared to traditional neural network models. We present an interactive demonstration of a SNN-based smart watchdog circuit capable of real-time monitoring and detection of errors during program execution in a modern RISC-V processor. The smart watchdogs performance is demonstrated by monitoring the RISC-V core running a control task resembling a safety-critical application, where demo-attendees can inject faults into the program counter register and witness the detection of errors and how control flow errors impacts the motor operation. The demo permits various fault injection patterns, i.e. bit flips and stuck at zero/one faults.

Modern micro-processors face reliability challenges due to manufacturing defects, aging or when operating in harsh environments like deep-sea or space. Watchdog mechanisms are essential for detecting both permanent and transient faults, but they must exhibit minimal overheads in terms of power and area consumption. Nonetheless, additional research is required to ensure the dependability of the watchdog circuit as if compromised, could pose a significant threat to the system. This paper proposes a smart watchdog paradigm based on spiking neural networks (SNNs) that could realise a reliable, low power and area efficient solution. The smart watchdog presented in this paper was trained to monitor control flow at the execute stage of a RISC-V processor with results showing high fault coverage of 98%, independent of the software application executed. The smart watchdog was able to detect faults not recognised by the trap handler of the RISC-V core. An FPGA implementation of the smart watchdog validates the in-circuit fault detection capability when deployed with a RISC-V processor.

The motility of microglia involves intracellular signaling pathways that are predominantly controlled by changes in cytosolic Ca2+ and activation of PI3K/Akt (phosphoinositide-3-kinase/protein kinase B). In this letter, we develop a novel biophysical model for cytosolic Ca2+ activation of the PI3K/Akt pathway in microglia where Ca2+ influx is mediated by both P2Y purinergic receptors (P2YR) and P2X purinergic receptors (P2XR). The model parameters are estimated by employing optimization techniques to fit the model to phosphorylated Akt (pAkt) experimental modeling/in vitro data. The integrated model supports the hypothesis that Ca2+ influx via P2YR and P2XR can explain the experimentally reported biphasic transient responses in measuring pAkt levels. Our predictions reveal new quantitative insights into P2Rs on how they regulate Ca2+ and Akt in terms of physiological interactions and transient responses. It is shown that the upregulation of P2X receptors through a repetitive application of agonist results in a continual increase in the baseline [Ca2+], which causes the biphasic response to become a monophasic response which prolongs elevated levels of pAkt.

Failure of large complex structures such as buildings and bridges can have monumental repercussions such as human mortality, environmental destruction and economic consequences. It is therefore paramount that detection of structural damage or anomalies are identified and managed early. This highlights the need to develop automated Structural Health Monitoring (SHM) systems that can continuously allow the safety status of structures to be determined, even in the worst and most isolated conditions, to ultimately help prevent destruction and save lives. Signal processing is a crucial step to detecting structural anomalies and recent work demonstrates the opportunities for neural networks, however the encoding of data for SHM requires the extraction of features due to often, noisy data. This paper focuses on feature extraction methods for artificial neural networks (ANNs) and spiking neural networks (SNNs) and aims to identify bespoke features which enable SNNs to encode data and perform the classification of anomalies. Results show that extraction of particular features in large real-world applications improve the classification accuracy of SNNs.

Regulation of cytosolic calcium (Ca2+) dynamics is fundamental to microglial function. Temporal and spatial Ca2+ fluxes are induced from a complicated signal transduction pathway linked to brain ionic homeostasis. In this paper, we develop a novel biophysical model of Ca2+ and sodium (Na+) dynamics in human microglia and evaluate the contribution of purinergic receptors (P2XRs) to both intracellular Ca2+ and Na+ levels in response to agonist/ATP binding. This is the first comprehensive model that integrates P2XRs to predict intricate Ca2+ and Na+ transient responses in microglia. Specifically, a novel compact biophysical model is proposed for the capture of whole-cell patch-clamp currents associated with P2X4 and P2X7 receptors, which is composed of only four state variables. The entire model shows that intricate intracellular ion dynamics arise from the coupled interaction between P2X4 and P2X7 receptors, the Na+/Ca2+ exchanger (NCX), Ca2+ extrusion by the plasma membrane Ca2+ ATPase (PMCA), and Ca2+ and Na+ leak channels. Both P2XRs are modelled as two separate adenosine triphosphate (ATP) gated Ca2+ and Na+ conductance channels, where the stoichiometry is the removal of one Ca2+ for the hydrolysis of one ATP molecule. Two unique sets of model parameters were determined using an evolutionary algorithm to optimise fitting to experimental data for each of the receptors. This allows the proposed model to capture both human P2X7 and P2X4 data (hP2X7 and hP2X4). The model architecture enables a high degree of simplicity, accuracy and predictability of Ca2+ and Na+ dynamics thus providing quantitative insights into different behaviours of intracellular Na+ and Ca2+ which will guide future experimental research. Understanding the interactions between these receptors and other membrane-bound transporters provides a step forward in resolving the qualitative link between purinergic receptors and microglial physiology and their contribution to brain pathology.

Spiking astrocyte neural networks (SANN) are a new computational paradigm that exhibit enhanced self-adapting and reliability properties. The inclusion of astrocyte behaviour increases the computational load and critically the number of connections, where each astrocyte typically communicates with up to 9 neurons (and their associated synapses) with feedback pathways from each neuron to the astrocyte. Each astrocyte cell also communicates with its neighbouring cell resulting in a significant interconnect density. The substantial level of parallelisms in SANNs lends itself to acceleration in hardware, however, the challenge in accelerating simulations of SANNs firmly resides in scalable interconnect and the ability to inject and retrieve data from the hardware. This paper presents a novel multi-FPGA acceleration architecture, AstroByte, for the speedup of SANNs. AstroByte explores Networks-on-Chip (NoC) routing mechanisms to address the challenge of communicating both spike event (neuron data) and numeric (astrocyte data) across significant interconnect pathways between astrocytes and neurons. AstroByte also exploits the NoC interconnect to inject data and retrieve runtime data from the accelerated SANN simulations. Results show that AstroByte can simulate SANN applications with speedup factors of between xl62 -xl88 over Matlab equivalent simulations.

Astrocytes can affect neuronal communication by controlling extracellular ionic concentration levels. In the hippocampus, astrocytes have an intimate relationship with neuronal synapses, enwrapping the synapse tightly to prevent chemical diffusion between synapses, a phenomenon known as semi-isolated synapses. Calcium (Ca2+) is known to enhance neurotransmitter release at excitatory synapses and release is dependent on levels of Ca2+in the perisynaptic environment. Astrocytes have a great influence on Ca2+levels at semi-isolated synapses, thus, they can affect neuronal transmission through control of synaptic Ca2+levels. The perisynaptic astrocytic processes that semi-isolate synapses are exceedingly thin, typically having a diameter less than 100nm, therefore, these processes are most likely devoid of intracellular organelles and therefore, Ca2+stores. Astrocytes possess many transmembrane proteins that can traffic Ca2+into and out of the cell, with the plasma membrane ATPase and the sodium/calcium exchanger being the main transporters capable of carrying Ca2+across the plasma membrane in large quantities.The main aim of this research is to capture a more complete astroglial Ca2+pathway as this may be important for understanding biological processes involving Ca2+such as synaptic transmission, plasticity and ultimately learning. We use a computational approach to capture the ionic dynamics in a semi-isolated synapse, with particular focus on Ca2+dynamics. The model presented here is an extension of a recently published model that hypothesises the formation of Ca2+microdomains in perisynaptic astrocytes. We take this hypothesis further and show that these Ca2+microdomains can act as a local supply of Ca2+to the synaptic cleft during periods of sustained excitability.

Networks-on-Chip (NoC) is the most modular and scalable solution for next generation hardware communication where significant data traffic loads are shared across many communication paths. One key challenge in maximising NoC performance is traffic congestion. The management of congestion at the earliest stage can significantly minimize the impact on NoC throughput. Prediction of NoC congestion offers a pre-emptive strategy in maximising NoC throughput. This paper proposes a novel spiking neural network (SNN) approach to prediction of traffic congestion. The proposed SNN exploits the temporal nature of the traffic to identify congestion patterns. The proposed SNN explores two models and both are trained and evaluated to predict local congestion 30 clock cycles in advance of occurring. Results shows that the SNN predictor utilizes 9 times less hardware area than previous approaches and can achieved up to 96.59% in accuracy.

It is now known that astrocytes modulate the activity at the tripartite synapses where indirect signaling via the retrograde messengers, endocannabinoids, leads to a localized self-repairing capability. In this paper, a self-repairing spiking astrocyte neural network (SANN) is proposed to demonstrate a distributed self-repairing capability at the network level. The SANN uses a novel learning rule that combines the spike-timing-dependent plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules (hereafter referred to as the BSTDP rule). In this learning rule, the synaptic weight potentiation is not only driven by the temporal difference between the presynaptic and postsynaptic neuron firing times but also by the postsynaptic neuron activity. We will show in this paper that the BSTDP modulates the height of the plasticity window to establish an input-output mapping (in the learning phase) and also maintains this mapping (via self-repair) if synaptic pathways become dysfunctional. It is the functional dependence of postsynaptic neuron firing activity on the height of the plasticity window that underpins how the proposed SANN self-repairs on the fly. The SANN also uses the coupling between the tripartite synapses and γ -GABAergic interneurons. This interaction gives rise to a presynaptic neuron frequency filtering capability that serves to route information, represented as spike trains, to different neurons in the subsequent layers of the SANN. The proposed SANN follows a feedforward architecture with multiple interneuron pathways and astrocytes modulate synaptic activity at the hidden and output neuronal layers. The self-repairing capability will be demonstrated in a robotic obstacle avoidance application, and the simulation results will show that the SANN can maintain learned maneuvers at synaptic fault densities of up to 80% regardless of the fault locations.

Forest fires is one of the main causes of environmental degradation and its detection and forecasting is challenging. A novel method of forest fire detection based on spiking neural networks is proposed in this paper. Data obtained from controlled experiments are used as input training samples and a detection model is established by considering the factors of temperature, humidity, carbon monoxide concentration, wind speed and wind direction. Experimental results show that the spiking neural network can achieve a detection accuracy of ∼91%, and therefore provides a better power/accuracy trade-off against existing approaches.

Spiking Astrocyte-neuron Networks (SANNs) model the adaptive/repair feature of the human brain. They integrate astrocyte cells with spiking neurons to facilitate a distributed and fine-grained self-repair capability at the synapse level. SANNs are more complex with the addition of astrocyte cells and require longer simulation times, as they are dynamic over much longer time-scales than traditional neural networks. Therefore, dedicated FPGA accelerators offer reductions in simulation times. To support the acceleration of SANNs, the capability of fault injection to synapses and monitoring significant levels of neuron and astrocyte data for off-chip transmission to PC-based analysis, are required. This paper presents an FPGA-based monitoring platform (FMP) for injecting faults and capturing and analyzing data acquired from the SANN FPGA accelerator, Astrobyte. The FMP uses custom logic and a NIOS II based system to control fault injection and data monitoring on the FPGA. Results show accurate accelerated simulations of fault injection scenarios using FMP with speedups up to 65 times greater compared with equivalent Matlab implementations.

A biophysical model that captures molecular homeostatic control of ions at the perisynaptic cradle (PsC) is of fundamental importance for understanding the interplay between astroglial and neuronal compartments. In this paper, we develop a multi-compartmental mathematical model which proposes a novel mechanism whereby the flow of cations in thin processes is restricted due to negatively charged membrane lipids which result in the formation of deep potential wells near the dipole heads. These wells restrict the flow of cations to "hopping" between adjacent wells as they transverse the process, and this surface retention of cations will be shown to give rise to the formation of potassium (K+) and sodium (Na+) microdomains at the PsC. We further propose that a K+ microdomain formed at the PsC, provides the driving force for the return of K+ to the extracellular space for uptake by the neurone, thereby preventing K+ undershoot. A slow decay of Na+ was also observed in our simulation after a period of glutamate stimulation which is in strong agreement with experimental observations. The pathological implications of microdomain formation during neuronal excitation are also discussed.

The ability of astrocytes to rapidly clear synaptic glutamate and purposefully release the excitatory transmitter is critical in the functioning of synapses and neuronal circuits. Dysfunctions of these homeostatic functions have been implicated in the pathology of brain disorders such as mesial temporal lobe epilepsy. However, the reasons for these dysfunctions are not clear from experimental data and computational models have been developed to provide further understanding of the implications of glutamate clearance from the extracellular space, as a result of EAAT2 downregulation: although they only partially account for the glutamate clearance process. In this work, we develop an explicit model of the astrocytic glutamate transporters, providing a more complete description of the glutamate chemical potential across the astrocytic membrane and its contribution to glutamate transporter driving force based on thermodynamic principles and experimental data. Analysis of our model demonstrates that increased astrocytic glutamate content due to glutamine synthetase downregulation also results in increased postsynaptic quantal size due to gliotransmission. Moreover, the proposed model demonstrates that increased astrocytic glutamate could prolong the time course of glutamate in the synaptic cleft and enhances astrocyte-induced slow inward currents, causing a disruption to the clarity of synaptic signalling and the occurrence of intervals of higher frequency postsynaptic firing. Overall, our work distilled the necessity of a low astrocytic glutamate concentration for reliable synaptic transmission of information and the possible implications of enhanced glutamate levels as in epilepsy.

Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism in the human brain, where spiking neurons provide direct and indirect feedbacks to presynaptic terminals. These feedbacks modulate the synaptic transmission probability of release (PR). When synaptic faults occur, the neuron becomes silent or near silent due to the low PR of synapses; whereby the PRs of remaining healthy synapses are then increased by the indirect feedback from the astrocyte cell. In this paper, a novel hardware architecture of Self-rePAiring spiking Neural NEtwoRk (SPANNER) is proposed, which mimics this self-repairing capability in the human brain. This paper demonstrates that the hardware can self-detect and self-repair synaptic faults without the conventional components for the fault detection and fault repairing. Experimental results show that SPANNER can maintain the system performance with fault densities of up to 40%, and more importantly SPANNER has only a 20% performance degradation when the self-repairing architecture is significantly damaged at a fault density of 80%.

We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

This paper presents the Pi-puck extension board - an interface between the e-puck robot platform and a Raspberry Pi single-board computer that enhances the processing power, memory capacity, and networking capabilities of the robot at a low cost. It allows high-level control algorithms, wireless communication, and computationally expensive operations such as real-time image processing to be handled by a Raspberry Pi, while the e-puck's microcontroller deals with low-level motor control and sensor interfacing. Although two similar extension boards for the e-puck robot platform already exist, they are now out-dated and expensive in comparison. Our open-source hardware design and supporting software infrastructure offer an inexpensive upgrade to the e-puck robot, transforming it into the Pi-puck - a modern and flexible new platform for mobile robotics research.

A self-repairing robot utilising a spiking astrocyte-neuron network is presented in this paper. It uses the output spike frequency of neurons to control the motor speed and robot activation. A software model of the astrocyte-neuron network previously demonstrated self-detection of faults and its self-repairing capability. In this paper the application demonstrator of mobile robotics is employed to evaluate the fault-tolerant capabilities of the astrocyte-neuron network when implemented in a hardware-based robotic car system. Results demonstrated that when 20% or less synapses associated with a neuron are faulty, the robot car can maintain system performance and complete the task of forward motion correctly. If 80% synapses are faulty, the system performance shows a marginal degradation, however this degradation is much smaller than that of conventional fault-tolerant techniques under the same levels of faults. This is the first time that astrocyte cells merged within spiking neurons demonstrates a self-repairing capabilities in the hardware system for a real application.

A Self-rePAiring spiking Neural NEtwoRk (SPANNER) hardware architecture is presented in this paper. It is based on a software model of an astrocyte-neuron network which previously demonstrated the ability to self-detect faults and self-repair autonomously. Experimental results in this paper show that when faults occur at the synapse, remaining healthy synapses of the same neuron are enhanced by the feedback from the astrocyte, which enables system functionality to be maintained. This is the first time that astrocyte cells merged within spiking neurons demonstrate a self-repairing capability in hardware. This repair capability achieves a much more finegrained repair capability in hardware compared to the conventional fault tolerance techniques.

A key requirement for modern large scale neuromorphic systems is the ability to detect and diagnose faults and to explore self-correction strategies. In particular, to perform this under area-constraints which meet scalability requirements of large neuromorphic systems. A bio-inspired online fault detection and self-correction mechanism for neuro-inspired PID controllers is presented in this paper. This strategy employs a fault detection unit for online testing of the PID controller; uses a fault detection manager to perform the detection procedure across multiple controllers, and a controller selection mechanism to select an available fault-free controller to provide a corrective step in restoring system functionality. The novelty of the proposed work is that the fault detection method, using synapse models with excitatory and inhibitory responses, is applied to a robotic spike-based PID controller. The results are presented for robotic motor controllers and show that the proposed bio-inspired self-detection and self-correction strategy can detect faults and re-allocate resources to restore the controller's functionality. In particular, the case study demonstrates the compactness (~1.4% area overhead) of the fault detection mechanism for large scale robotic controllers.

Abstract An authentication strategy is proposed in this paper for embedded system software copyright protection. It employs a chaotic coupled map lattices (CML) system to generate the pseudo‐random numbers, which are used to construct message authentication codes (MAC) for embedded system authentication. The CML has multiple lattices where the adjacent lattices have coupled effect. When the system initial condition (e.g. lattice values and system parameters) has a marginal change, the output will have a significant change. Therefore, the proposed scheme is highly secure as the final MAC is almost impossible to be compromised. The experiment is conducted on the platform of field programmable gate array, and its corresponding results demonstrate that the proposed strategy achieved a good security performance, a high computing speed and a relatively low area overhead. Copyright © 2015 John Wiley & Sons, Ltd.

It has been shown that brain-like self-repair can arise from the interactions between neurons and astrocytes where endocannabinoids are synthesized and released from active neurons. This retrograde messenger feeds back to local synapses directly and indirectly to distant synapses via astrocytes. This direct/indirect feedback of the endocannabinoid retrograde messenger results in the modulation of the probability of release (PR) at synaptic sites. When synapses fail, there is a corresponding falloff in the firing activity of the associated neurons, and hence the strength of the direct feedback messenger diminishes. This triggers an increase in PR of healthy synapses, due to the indirect messenger from other active neurons, which is the catalyst for the repair process. In this paper, the repair process is implemented by developing a new learning rule that captures the spike-timing-dependent plasticity and Bienenstock, Cooper, and Munro learning rules. The rule is activated by the increase in PR and results in a potentiation of the weight values, which reestablishes the firing activity of neurons. In addition, this self-repairing mechanism is extended to network-level repair where astrocyte to astrocyte communications are implemented using a linear gap junction model. This facilitates the implementation of an astroglial syncytium involving multiple astrocytes, which relays the indirect feedback messenger to distant neurons: each astrocyte is bidirectionally coupled to neurons. A detailed and comprehensive set of results with analysis is presented demonstrating repair at both cellular and network levels.

Spike timing dependent plasticity (STDP) forms the basis of learning within neural networks. STDP allows for the modification of synaptic weights based upon the relative timing of pre- and post-synaptic spikes. A compact circuit is presented which can implement STDP, including the critical plasticity window, to determine synaptic modification. A physical model to predict the time window for plasticity to occur is formulated and the effects of process variations on the window is analyzed. The STDP circuit is implemented using two dedicated circuit blocks, one for potentiation and one for depression where each block consists of 4 transistors and a polysilicon capacitor. SpectreS simulations of the back-annotated layout of the circuit and experimental results indicate that STDP with biologically plausible critical timing windows over the range from [email protected]?s to 100ms can be implemented. Also a floating gate weight storage capability, with drive circuits, is presented and a detailed analysis correlating weights changes with charging time is given.

This paper proposes a spiking-neural-network-based robot controller inspired by the control structures of biological systems. Information is routed through the network using facilitating dynamic synapses with short-term plasticity. Learning occurs through long-term synaptic plasticity which is implemented using the temporal difference learning rule to enable the robot to learn to associate the correct movement with the appropriate input conditions. The network self-organizes to provide memories of environments that the robot encounters. A Pioneer robot simulator with laser and sonar proximity sensors is used to verify the performance of the network with a wall-following task, and the results are presented.

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.

The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33×109spikes/second), and synthesis results using 65-nm CMOS technology demonstrate low cost area (0.587mm2) and power consumption (13.16mW @100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.

A compact implementation of a dynamic charge transfer synapse cell, capable of implementing synaptic depression, is presented. The cell is combined with a simple current mirror summing node to produce biologically plausible postsynaptic potentials (PSPs). A single charge packet is effectively transferred from the synapse to the summing node, whenever a presynaptic pulse is applied to one of its terminals. The charge packet is "weighted" by a voltage applied to the second terminal of the synapse. A voltage applied to the third terminal determines the charge recovery time in the synapse, which can be adjusted over several orders of magnitude. This voltage determines the paired pulse ratio for the synapse. The fall time of the PSP is also adjustable and is set by the gate voltage of a metal-oxide-semiconductor field-effect transistor operating in subthreshold. Results extracted from chips fabricated in a 0.35-μm complementary metal-oxide-semiconductor process, alongside theoretical and simulation results, confirm the ability of the cell to produce PSPs that are characteristic of real synapses. The concept addresses a key requirement for scalable hardware neural networks.

In this paper, a spiking neural network (SNN) architecture to simulate the sound localization ability of the mammalian auditory pathways using the interaural intensity difference cue is presented. The lateral superior olive was the inspiration for the architecture, which required the integration of an auditory periphery (cochlea) model and a model of the medial nucleus of the trapezoid body. The SNN uses leaky integrate-and-fire excitatory and inhibitory spiking neurons, facilitating synapses and receptive fields. Experimentally derived head-related transfer function (HRTF) acoustical data from adult domestic cats were employed to train and validate the localization ability of the architecture, training used the supervised learning algorithm called the remote supervision method to determine the azimuthal angles. The experimental results demonstrate that the architecture performs best when it is localizing high-frequency sound data in agreement with the biology, and also shows a high degree of robustness when the HRTF acoustical data is corrupted by noise.

Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.

This paper investigates how layers of spiking neurons can be connected using lateral inhibition in different ways to bring about synchrony, reduce noise, and extract or enhance features. To illustrate the effects of the various connectivity regimes spectro-temporal speech data in the form of isolated digits is employed. The speech samples are preprocessed using the Lyon's Passive Ear cochlear model, and then encoded into tonotopically arranged spike arrays using the BSA spiker algorithm. The spike arrays are then subjected to various lateral inhibitory connectivity regimes configured by two connectivity parameters, namely connection length and neighbourhood size. The combination of these parameters are demonstrated to produce various effects such as transient synchrony, reduction of noisy spikes, and sharpening of spectro-temporal features.

Recent work has shown that astrocytes are capable of bidirectional communication with neurons which leads to modulation of synaptic activity. Moreover, indirect signaling pathways of retrograde messengers such as endocannabinoids lead to modulation of synaptic transmission probability. In this paper we hypothesize that this signaling underpins fault tolerance in the brain. In particular, faults manifest themselves in silent or near silent neurons, which is caused by low transmission probability synapses, and the enhancement of the transmission probability of a “faulty” synapse by indirect retrograde feedback is the repair mechanism. Furthermore, based on recent findings we present a model of self repair at the synaptic level, where retrograde signaling via astrocytes increases the probability of neurotransmitter release at damaged or low transmission probability synapses. Although our model is still at the embryo stage, results presented are encouraging and highlight a new research direction on brain-like self repair.

This study investigates the computing capabilities and potential applications of neural oscillators to grey scale and colour image segmentation, an important task in image understanding and object recognition. A proposed neural system that combines the synergy between neural oscillators and Kohonen self-organising maps (SOM) is presented. Colour image segmentation is achieved through temporal synchronisation of neural oscillators that are mapped to pixels of the same object. Neurons are organised in a two-dimensional grid and are locally connected through excitatory connections and globally connected to a common inhibitor. Self-organising maps form the basis of a colour reduction system whose output is fed to a 2D grid of neural oscillators such as each neuron is mapped to a pixel of the input image. Both chromatic and local spatial features are used. The proposed system is simulated in Matlab and its demonstration on real world colour images shows promising results and the emergence of a new bio-inspired approach for colour image segmentation.

This paper presents a spiking neural network-based investigation of the issues associated with extraction of onset, offset, and coincidental firing features from spectro-temporal data. Speech samples containing spoken isolated digits from the TI46 database are employed to demonstrate the way in which these features can be extracted using leaky integrate-and-fire spiking neurons with dynamic synapses. The flexibility that the additional synaptic parameters in the neuron model provides, is demonstrated to be essential for onset, offset and coincidental firing extraction. Recurrency and the interaction between excitation and inhibition together with latency is demonstrated to be a viable means of extracting offset features. The effects of lateral inhibition and in particular its ability to induce transient synchrony in spike firing is evaluated. In particular, by defining a connection length parameter, and hence a neighbourhood size, synchronous firing is shown to gradually develop as connection length and neighbourhood size increases. Finally, the implications for this connectivity in spiking neural networks and its potential for learning spectral and spatio-temporal patterns via the formation of receptive fields is discussed.

This paper presents a Spiking Neural Network (SNN) architecture for mobile robot navigation. The SNN contains 4 layers where dynamic synapses route information to the appropriate neurons in each layer and the neurons are modeled using the Leaky Integrate and Fire (LIF) model. The SNN learns by self-organizing its connectivity as new environmental conditions are experienced and consequently knowledge about its environment is stored in the connectivity. Also a novel feature of the proposed SNN architecture is that it uses working memory, where present and previous sensor states are stored. Results are presented for a wall following application.

This paper proposes a supervised training algorithm for Spiking Neural Networks (SNNs) which modifies the Spike Timing Dependent Plasticity (STDP)learning rule to support both local and network level training with multiple synaptic connections and axonal delays. The training algorithm applies the rule to two and three layer SNNs, and is benchmarked using the Iris and Wisconsin Breast Cancer (WBC) data sets. The effectiveness of hidden layer dynamic threshold neurons is also investigated and results are presented.

This paper presents a synaptic weight association training (SWAT) algorithm for spiking neural networks (SNNs). SWAT merges the Bienenstock-Cooper-Munro (BCM) learning rule with spike timing dependent plasticity (STDP). The STDP/BCM rule yields a unimodal weight distribution where the height of the plasticity window associated with STDP is modulated causing stability after a period of training. The SNN uses a single training neuron in the training phase where data associated with all classes is passed to this neuron. The rule then maps weights to the classifying output neurons to reflect similarities in the data across the classes. The SNN also includes both excitatory and inhibitory facilitating synapses which create a frequency routing capability allowing the information presented to the network to be routed to different hidden layer neurons. A variable neuron threshold level simulates the refractory period. SWAT is initially benchmarked against the nonlinearly separable Iris and Wisconsin Breast Cancer datasets. Results presented show that the proposed training algorithm exhibits a convergence accuracy of 95.5% and 96.2% for the Iris and Wisconsin training sets, respectively, and 95.3% and 96.7% for the testing sets, noise experiments show that SWAT has a good generalization capability. SWAT is also benchmarked using an isolated digit automatic speech recognition (ASR) system where a subset of the TI46 speech corpus is used. Results show that with SWAT as the classifier, the ASR system provides an accuracy of 98.875% for training and 95.25% for testing.

FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.

We present a programmable dynamic Charge Transfer Synapse (CTS) in a single semiconductor device. The CTS comprises a Metal Oxide Semiconductor (MOS) transistor operating in subthreshold and two MOS capacitors in proximity to the transistor. One of the capacitors is permanently biased in strong inversion where the associated density of charge in the well implements the weighting. When a presynaptic spike is applied to the gate of the second MOS capacitor the charge density in the well falls producing a current spike at the output. The amplitude of the spike is correlated with the equilibrium charge density in the well, which is controlled by the associated gate voltage. Aggregation of spikes from an array of CTSs is achieved by using a current mirror configuration whose output postsynaptic potential can be used to stimulate a point neuron circuit. The function of the MOS transistor is to restore the charge in the well where the duration of this process is dictated by the associated gate voltage. Therefore, the synapse is capability of operating in the facilitating state over a large frequency range. The CTS is compact and since it operates in transient mode, its power consumption is negligible. Simulation results are presented which clearly demonstrate its operation.

The work presented in this paper merges the Bienenstock-Cooper-Munro (BCM) learning rule with Spike Timing Dependent Plasticity (STDP) to develop a training algor ithm for a Spiking Neural Network (SNN), stimulated using spike trains. The BCM rule is utilised to modulate the height of the plasticity window, associated with STDP. The SNN topology uses a single training neuron in the training phase where all classes are passed to this neuron, and the associated weights are subsequently mapped to the classifying output neurons: the weights are proportionally distributed across the output neurons to reflect similarities in the input data. The training algorithm also includes both exhibitory and inhibitory facilitating dynamic synapses that create a frequency routing capability allowing the information presented to the network to be routed to different hidden layer neurons. A variable neuron threshold level simulates the refractory period. The network is benchmarked against the non-linearly separable IRIS data set problem and results presented in the paper show that the proposed training algorithm exhibits a convergence accuracy comparable to other SNN training algorithms.

Sound localisation is defined as the ability to identify the position of a sound source. The brain employs two cues to achieve this functionality for the horizontal plane, interaural time difference (ITD) by means of neurons in the medial superior olive (MSO) and interaural intensity difference (IID) by neurons of the lateral superior olive (LSO), both located in the superior olivary complex of the auditory pathway. This paper presents spiking neuron architectures of the MSO and LSO. An implementation of the Jeffress model using spiking neurons is presented as a representation of the MSO, while a spiking neuron architecture showing how neurons of the medial nucleus of the trapezoid body interact with LSO neurons to determine the azimuthal angle is discussed. Experimental results to support this work are presented.

A neuron circuit is presented which can mimic the operation of a spiking neuron cell. A current mirror configuration allows the temporal summing of synaptic inputs, which are subsequently stored as a charge packet on the gate of a CMOS inverter: the inverter is coupled to a second inverter and feedback is used to facilitate re-setting the cell after firing. Charge leakage from the gate of the inverter, via a reverse biased p-n junction, provides a membrane decay time constant comparable with what is observed in biological neurons. Breadboard experiments and simulation results are presented to demonstrate the functionality of the neuron circuit.

A charge-coupled silicon synapse with a floating diffusion output is proposed as the basis for a new electronic, spiking neuron cell. The synapse is formed by a two-stage charge transfer device with the weight function stored in a floating gate over the first stage. The output of the synapses feeds into the multi-gate inputs of a MOSFET which themselves capacitively couple onto a common floating gate. This MOSFET provides a summing action and so acts as a point neuron. Thermal generation within the synaptic device, causes relaxation of the signals and this can be tailored to provide realistic PostSynaptic Potential (PSP) dependencies. Simulation results show that this architecture can generate a PSP that effectively mimics the spiking behaviour of real synapses. The cell is highly compact and intrinsically low power and so offers the potential for biologically plausible Spiking Neural Networks (SNNs) in hardware.

This paper presents an extension of previous work whereby the Spike Timing Dependant Plasticity (STDP) rule was used to train a two layer Spiking Neural Network (SNN). In that work a supervised training algorithm was developed using an STDP based rule that affected weights both locally and at network level. This work extends the rule to a three layer network with multiple inter-neuron excitatory synaptic connections and associated delays. The network utilises dynamic thresholds to facilitate an association between spatial patterns in the input data and classes. The algorithm is benchmarked using nonlinearly separable classification problems and results show that the three layer network exhibits a significant improvement over the two layer.

A novel inter-neuron communications method for increased scalability of Spiking Neural Networks (SNNs) is presented. Capacitive coupling is used as the communication medium with spike functions replaced by oscillatory bursts. The dependency of the coupling signals between neuron layers as a function of neuron density, frequency and track loading is predicted. High Q decoding filters and accurate frequency matching between transmitting neurons and receiving synapses was achieved using band pass filters. Micro-Electro-Mechanical Systems (MEMS) were used in the filter circuits and burst oscillators because of their high Q values. The method of fabricating the on-chip coupling capacitors and associated oscillator/filter circuits is discussed.

Abstract. This paper details a new object-oriented methodology that permits a unified modelling language (UML) behavioural representation of analogue circuits at system level. The proposed method demonstrates a novel approach to the problem of behavioural representation of an analogue topology, by constructing a consistent set of rules for automated mapping of the UML model to a VHDL-AMS specification. The VHDL-AMS specification enables behavioural simulation of the UML model and the methodology is validated using an analogue subsystem level application.