Electromigration (EM) is crucial for interconnect reliability. This article introduces the implementation and application of CacheEM which targets SRAM cache memory aging due to EM. CacheEM is based on a comprehensive framework including five parts: 1) microprocessor emulation; 2) memory cell array activity extraction; 3) computation of currents in segments of long complex interconnect structures; 4) evaluation of the time-dependent hydrostatic stress and the resistance shift of interconnects; and 5) characterization of the EM lifetime distribution of interconnects in the cache memory. The first two steps (top-down) are implemented with gem5 and cache simulation, respectively. These simulators export the number of read and write operations for each cell of a cache memory in a microprocessor after running benchmarks. Then, based on the number of operations and the currents corresponding to each operation, CacheEM calculates the equivalent current distribution in each interconnect segment as the third step (bottom-up). The currents due to read and write operations are stored in models which have been pretrained with a regression algorithm. These models provide accurate predictions of the corresponding currents under various parameter settings, such as temperature, supply voltage, and gate length. Afterward, the samples of time-dependent hydrostatic stress and the resistance shift in each interconnect segment are computed while incorporating the variations of the effective activation energy and critical stress. The EM lifetime distribution of the cache memory is extracted using predefined threshold values. The impact of configuration parameters on EM reliability and performance of the SRAM cache is analyzed by comparing EM lifetime distributions.

This article describes a comprehensive framework for analysis of time-dependent performance-reliability degradation of an SRAM cache, considering cache configurations, process parameters and their variations, supply voltage, and aging. The framework consists of three parts: microprocessor emulation, activity extraction, and evaluation of performance-reliability metrics. Evaluation of performance-reliability metrics is implemented with a prediction engine involving regression models for the metrics, which evaluates degradation due to various wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and random telegraph noise (RTN). The regression models not only enable more than 100× faster computation compared with SPICE simulations but also protect intellectual property. This framework has been applied to study how SRAM instruction cache (I-Cache) configurations, cell structure, inclusion of RTN and gate length variation, voltage scaling, and stress time affect the performance and reliability parameters, such as access time, leakage power, critical charge ( Qcrit), and static noise margin (SNM). We have also studied the impact of configuration parameters on the soft error rate (SER) and the hit rate of the I-Cache, and the impact of single error correction and double error detection (SECDED) error correcting codes (ECCs).

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions.

Bias temperature instability (BTI), hot carrier injection (HCI), gate-oxide time-dependent dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of the deeply scaled transistors and the overall circuit reliability. These front-end wearout mechanisms are especially acute in the static random access memory (SRAM) cells of first-level (L1) caches, which are crucial for the performance of microprocessors due to frequent accesses. This article presents a methodology to analyze cache reliability degradation due to the combined effect of BTI, HCI, GTDDB, and RTN for different cache configurations, including variations due to associativity, cache line size, cache size, and the error-correcting codes (ECCs). Time-zero variability due to process and environmental parameters are also considered. First, we analyze how each wearout mechanism affects reliability degradation. Then we analyze the relationship between reliability (probability of failure) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, which determine cell array activity, characterized by the duty cycle, toggle rate, temperature, and supply voltage distributions of cells. Insights on the performance-reliability tradeoff are provided for cache designers.

Circuits may fail in the field due to a wide variety of failure modes. If there are frequent failures in the field, circuits are returned to the manufacturer, and the causes of failure must be identified. The challenge is that wearout mechanisms are confounded in circuit and system-level failure data. Using such failure data, it is often hard to separate the underlying failure causes without time-consuming and expensive physical failure analysis. To distinguish the wearout mechanisms for each failure sample, we have developed a quick and low-cost methodology using maximum likelihood estimation and probability analysis to determine the origin of the failure distributions, region of error, and sorting accuracy. We apply our methodology to analyze the competing wearout mechanisms in 14nm FinFET ring oscillators, as an example, using simulation. We also consider the problem of Trojan detection.

Continuous memory technology scaling causes memory cells to be vulnerable to wearout. To ensure reliable operations of circuits and systems in the presence of wearout, we require accurate estimation of the lifetime of circuits and systems degraded by wearout. Since the conventional method of estimating circuit and system reliability degradation based on device-level accelerated life test (ALT) does not account for the tolerance of a circuit and a system to a wearout failure of a device, accelerated lifetime testing at the circuit and system level is necessary. For accurate estimation of system reliability using system-level ALT, we propose a method that optimizes the design of experiments for ALT. From significant observations from failure data statistics of system-level ALT with various stress conditions applied to the memory system of the Leon3 as a case study, we define acceptability regions for memory testing of each wearout mechanism. In addition, by analyzing errors in estimating Weibull parameters from system-level ALT, we develop a methodology that optimizes experimental designs in acceptability regions of each wearout mechanism to minimize such estimation errors in system-level ALT.

This paper presents a lifetime simulator for both Front-End-of-Line (FEOL) time dependent dielectric breakdown (TDDB) and the newly emerging Middle-of-Line (MOL) time dependent dielectric breakdown for FinFET technology. A lifetime assessment flow for digital circuits and microprocessors is proposed for the target wearout mechanisms, and its associated vulnerable feature extraction algorithms are discussed in detail. Our simulator incorporates the detailed electrical stress, temperature, linewidth of each standard cell within the digital circuit and microprocessor. Also, FEOL TDDB and MOL TDDB lifetimes are combined in the calculation of TDDB lifetime. Circuit designers can use the resulting lifetime information to guide and improve their circuits to make them more robust and reliable.

Safety critical systems need methodologies for chips to monitor their health in the field, so that the need for repairs can be determined during scheduled maintenance. Prior work provides health monitoring via detection of degradation. Since many wearout mechanisms provide no degradation signal, this paper proposes to use the embedded SRAM as a dynamic monitor of system health. The SRAM is monitored by detecting error correcting code (ECC) failures. The cause of ECC failures is diagnosed electrically with on-chip built-in self test (BIST). The time stamps and diagnosis data are combined to estimate process-level wearout model parameters. The extracted wearout model parameters are combined with system wearout simulation data and the memory bit failures recovered by error correcting codes (ECC) to estimate the remaining lifetime of the entire processor. The estimation of the remaining life is helpful in monitoring potential chip failures in the near future, to ensure safe operation.

Since memory cells tend to become more unreliable as technology scales down, to guarantee reliable operations of circuits/systems, prior to committing a design to manufacturing we need to accurately estimate the lifetime of a memory system by considering system usage. We propose to estimate the lifetime of a memory system using system-level accelerated life tests, where failures are detected with error-correcting codes. The difference from the standard approach to accelerated life tests of circuits/systems is that wearout simulation of circuits is used to select test conditions that are optimal for each wearout mechanism. In a case study, we investigate the reliability of a memory system in a microprocessor degraded by time-dependent dielectric breakdown, which is one of the major contributors to aging failures in modern computer systems. We estimate the probability of failure of the memory system at various stress conditions to define acceptability regions for TDDB for system-level accelerated life tests. The acceptability regions provide test conditions for each TDDB mechanism. We propose to use built-in self-test with fault detection via error-correcting codes during accelerated life tests, so that stress during accelerated test can track realistic usage patterns.

With the scaling of CMOS technology, negative bias temperature instability (NBTI) and gate oxide breakdown (GOBD) are serious issues for transistors. Normally, degradation due to NBTI and GOBD are modeled based on test structure data during process development and monitored with embedded test structures in product die. In this paper, we present a method to determine NBTI and GOBD model parameters through I/O measurements. This work targets products that do not include embedded test structures for wearout monitoring. The ground and power supply bounce signals are used for the calculation of delay and amplitude shifts, which in turn estimate threshold voltage shifts due to NBTI and leakage resistance decreases from gate dielectric degradation. From this data, the NBTI and GOBD parameters are estimated. We calculate the lifetime for each chip individually using calibrated NBTI and GOBD models. The methodology enables the extraction of NBTI and GOBD model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that are more or less vulnerable to NBTI and GOBD.

As dynamic random access memories (DRAMs) operate in the field, hard errors resulting from wearout occur. Unless corrected or repaired, hard errors halt normal operations, degrading the performance of a system and causing the replacement of memory modules. To improve performance and availability of memory modules, error-correcting codes (ECCs) are employed in a memory system. However, since recent field studies on DRAM errors have shown that a correctable error is highly likely to result in another error with the same address and in the same column or row, incorporating ECCs for mitigating not only soft errors but also hard errors in field operations is insufficient for ensuring reliable field operations. We propose a methodology that detects and repairs aging errors in DRAMs while operating in the field. We propose a methodology that reconfigures the remaining redundant resources after manufacturing-level repair into postpackage redundant resources. We also propose an ECC-assisted postpackage repair (PPR) flow that detects an error, identifies the type and location of the error, and invokes PPR for aging errors without built-in self-test/repair circuits. Employing a 2-GB ECC-dual in-line memory module of data-rate type three synchronous dynamic random access memories as a case study, we demonstrate that our PPR scheme improves the lifetime of DRAMs.

Bias Temperature Instability (BTI) and Hot Carrier Injections (HCI) are two of the main effects that increase a transistor's threshold voltage and further cause performance degradations. These two wearout mechanisms affect all transistors, but are especially acute in the SRAM cells of first-level (L1) caches, which are frequently accessed and are critical for microprocessor performance. This work studies the cache lifetimes due to the combined effect of BTI and HCI for different cache configurations, including variation in cache size, associativity, cache line size, and the replacement algorithm. The effect of process variations is also considered. We analyze the reliability (failure probability) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, and we provide essential insights on performance-reliability tradeoffs for cache designers.

Because of continuous scaling down to small dimensions, DRAM has become a main memory with high capacity and density. Because denser memories are likely to contain more errors, DRAM employs repair schemes that replace errors with good cells for yield enhancement of a memory. The conventional repair scheme covers only manufacturing-level errors. As DRAM wears out while operating in the field, to enhance the lifetime of a memory, we need to incorporate a post-package repair scheme into a memory system for repairing aging errors. In this paper, we propose a methodology that repairs aging errors in a memory during field operations. Using the memory yield and lifetime simulator, we evaluate the proposed repair method. Employing a 2GB DDR3 ECC-DIMM as a case study, we demonstrate that our post-package repair scheme improves the yield and the lifetime of a memory.

A method is proposed to detect failing cells due to bias temperature instability (BTI) in Static Random Access Memories (SRAMs) en route to failure. If potentially failing cells are detected prior to failure, SRAMs can be operated without failures, since the detection of potentially failing cells can trigger reconfiguration, given available memory redundancy. Using an experimentally verified BTI model, we study the performances of conventional 6T SRAM cells as a function of BTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation and with minimal overhead.

Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of BTI (NBTI and PBTI) and HCI on state-of-art microprocessors and to estimate microprocessor lifetimes due to each wearout mechanism. Our methodology finds the detailed electrical stress and the temperature of each device within a microprocessor system running a variety of standard benchmarks. Combining the electrical stress profiles, thermal profiles, and device-level models, we perform timing analysis on the critical paths of a microprocessor using our methodology to characterize the microprocessor performance degradation due to BTI and HCI and to estimate the lifetime distribution of logic blocks. In addition, we study dc noise margins in conventional 6T SRAM cells as a function of BTI and HCI degradation to estimate memory lifetime distributions. The lifetimes of memory blocks are then combined with the lifetimes of logic blocks to provide an estimate of the system lifetime distribution.

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field.

In this paper we present Memory Built-In Self-Test (MBIST) diagnosis methodologies for failure analysis of time-dependent breakdown due to gate oxide breakdown (GOBD) and backend time-dependent dielectric breakdown (BTDDB) in an SRAM array. First, a Built-In Self-Test (BIST) system and algorithm detect the breakdown mechanisms and identify the locations of the faulty sites in SRAM cells. Then, probabilities of failure are estimated for BTDDB and GOBD by matching the observed failure rate from BIST and the expected failure distribution functions from system simulations under realistic use scenarios, with different simulated failure rates for BTDDB and GOBD.

BIST for analog and RF circuits has been proposed many years ago and we are still chasing it. One school of thought is to have generic BIST components for input stimulus generation and output analysis and to use them in a plug-and-play fashion. Another school of thought is to develop dedicated circuits for each functionality and re-use the same blocks for the same functionality. A third approach is designing completely circuit-specific BIST for each primary circuit. The truth is ad-hoc examples of BIST have been around for years. However, there is no standardized way of implementing or inserting BIST for analog and RF circuits. The panelists, all experts in this domain, will share their view of the best way of implementing BIST for analog and RF circuits, if there is such a thing…

Back-end wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework that contains modules for back-end time-dependent dielectric breakdown, electromigration, and stress-induced voiding is proposed to analyze circuit layout geometries and interconnects to estimate state-of-the-art microprocessor lifetime due to each mechanism. Our methodology incorporates the detailed electrical stress temperature, linewidth, and cross-sectional areas of each interconnect/via within the microprocessor system. Different workloads are considered to evaluate aging effects in single-core microprocessors running applications with realistic use conditions.

Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between Δ Vthand signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of Δ Vthwe find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.

In this paper we present a Built-In Self Test (BIST) methodology for diagnosis of backend time-dependent dielectric breakdown (BTDDB), via voiding due to electromigration (EM), and stress-induced voiding (SIV) in SRAM cells. Our built-in self test methodology consists of two test procedures. First, faulty cells suffering from wearout mechanisms in the SRAM system are isolated. Then, these faulty cells are tested to determine the cause of wearout.

Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime because of backend dielectric breakdown is presented. It incorporates failures because of parallel tracks, the width effect, and field enhancement due to line ends. It also includes the operating temperature and activity.

Backend wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework which contains modules for backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze circuit layout geometries and interconnects to accurately estimate state-of-art microprocessor lifetime due to each mechanism. Our methodology incorporates the detailed electrical stress, temperature, linewidth and cross-sectional areas of each interconnect within the microprocessor system. We analyze several layouts using our methodology and highlight the lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units, using standard benchmarks.

Summary form only given. Negative bias temperature instability (NBTI) is one of the important reliability concerns that most drastically impacts circuit performances. In the digital domain, NBTI is addressed through adding reliability guard-bands on the maximum operating frequency of data paths and on the noise margins for memory cells. As a result, NBTI limits the performance/area optimization of digital circuits. Similarly, NBTI in analog circuits must be modeled and analyzed to ensure reasonable product lifetimes. The analysis of NBTI for analog circuits is more complex, since statistical NBTI causes not just performance degradation, but also increasing mismatch. Hence, randomness in the degradation process must be handled properly for analog circuits. In this work, we present a methodology to determine the impact of statistical NBTI on analog circuits. NBTI is due to the presence of interface traps at the gate oxide interface. It causes the threshold of PMOS devices to change.

In this work, we perform a comparative study of different wearout mechanisms affecting the state-of-art microprocessor systems. Taking into account the detailed thermal and electrical stress profiles, we present a methodology to accurately estimate the lifetime due to each mechanism. The lifetime-limiting wearout mechanisms are highlighted using standard benchmarks along with the reliability-critical microprocessor functional units.

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.

A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.

Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a technology node. Since NBTI degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration, given available memory redundancy. Using an experimentally verified NBTI model, we study DC noise margins in conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip NBTI monitoring scheme is presented that can be embedded within conventional cache designs without affecting normal device operation, enabling the prediction of cell failure before its occurrence.

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process after an initial gate leakage increase leading to device failure. It is proposed that if wearout can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration given available memory redundancy. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45 nm predictive technology. The DC margin trends (Read, Write and Retention) and access times (Read and Write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a practical definition for the hard-breakdown point of a cell. Using an on-chip PVT (process, voltage, and temperature) tolerant monitoring scheme, it has been shown that gradual wearout in SRAM cells, due to gate oxide breakdown, is detectible, and cell failure can be predicted before its occurrence.

A built-in self-test (BIST) circuit has been designed to test setup and hold times of I/O registers or buffers for memory interfaces. This method enables independent testing of setup and hold times without using an external tester, except to generate the reference clock. The circuit uses a delay-locked loop (DLL) to generate delayed clocks. It has been implemented with a 0.18-mum TSMC process (CM018). The accuracy in delay generation is within 40 ps, for delay measurements ranging from 300 to 700 ps. In order to achieve high accuracy, the BIST circuit requires frequency adjustment during test, combined with averaging over multiple test cycles. To do this in an efficient manner, the DLL in the BIST circuit has been designed for a wide lock range, from 150 to 400 MHz, and achieves lock in less than 0.05 mus. This paper describes the design in detail and evaluates its performance, together with test time and accuracy. It also shows how to use a low-resolution DLL to achieve high accuracy through frequency adjustment and averaging over multiple test cycles.

Increasing within-die variation, combined with larger numbers of critical and near-critical paths and higher operating frequencies, has increased the sensitivity of chips to path delay faults. A component of within-die variation comes from optical lithography, including the optical proximity effect, lens aberrations, and flare. This paper presents a methodology to generate test sets to diagnose these sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to a set of physical mechanisms originating from lithography. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose delay faults caused by lithography. The effectiveness of diagnosis is evaluated for ISCAS85 benchmark circuits.

A built-in-self-test (BIST) circuit for the test of a delay-locked loop circuit (DLL) is proposed. This circuit is based on a simple XNOR logic gate and uncalibrated delay lines to sample the output of the XNOR gate, so very little area overhead is introduced. In addition, no external stimulus is required for this BIST circuit, besides the ldquostart testrdquo signal. Fault simulation results show high fault coverage of structural faults, combined with some coverage of parametric variations.

As semiconductor technology advances into the nanoscale era and more functional blocks are added into systems-on-chip, the interface between circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers, are influencing both circuit performance and yield. As a result, design tools need to incorporate new factors. One important source of circuit-performance degradation comes from deterministic within-die variation from lithography imperfections and Cu-interconnect chemical-mechanical polishing (CMP). To determine how these within-die variations impact circuit performance, we need a new analysis tool. Thus, we have proposed a methodology to involve layout-dependent within-die variations in static timing analysis. Our methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark circuits in the presence of imperfect lithography and CMP variation

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 p m TSMC process (CM018) to test chip I/O speeds, specijkally, the setup and hold times of I10 registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also employs an eight-stage shift averaging voltagecontrolled delay line (VCDL) to improve the matching between delay stages and thus to equalize the delay of each individual stage. The locking failure or false locking problems are alleviated by using a start-control circuit. setup and hold times are two of the key metrics to evaluate the register or buffer's AC electrical characteristics. Therefore, it is important to test the specifications on setup and hold times. These tests will fail if the delays from the data inputs to the registers and from the clock input to the registers differ such that the data is not valid before (setup time) and after (hold time) the clock is asserted. This may happen due to delays in long buffered interconnect lines and in the clock tree. In order to satisfy the timing requirements, the delay in the clock tree must be larger than the delay for the data input by the setup time requirement, but not so large as to violate the hold time requirement.

In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 /spl mu/m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (/spl sim/25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximity-dependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

A divide-and-conquer algorithm for computing the parametric yield of large analog circuits is presented.The algorithm targets applications whose performance spreads could be highly nonlinear functions of a large numbers of stochastic process disturbances, and therefore can not easily be modeled by traditional response surface methods.This work addresses diculties with modeling by adaptively constructing the model piece by piece, namely, by eciently and recursively partitioning the disturbance space into several regions, each of which is then modeled by a local linear model.Local linear models are used because they are less sensitive to dimension than polynomial models.Moreover, the resulting model can be made to be more accurate in some regions compared to others.The number of simulations required in statistical modeling can therefore be reduced since only critical regions, which de ne the boundary of the feasible region in the space of process disturbances, are modeled highly accurately.The resulting models are then used as cheap surrogates for circuit simulation in Monte Carlo estimation of the parametric yield.Examples indicate the eciency and accuracy of this approach.

Analog testing is a difficult task without a clearcut methodology. Analog circuits are tested for satisfying their specifications, not for faults. Given the high cost of testing analog specifications, it is proposed that tests for analog circuits should be designed to detect faults. Therefore analog fault modeling is discussed. Based on an analysis of the types of tests needed for different types of faults, algorithms for fault-driven test set selection are presented. A major reduction in testing time should come from reducing the number of specification tests that need to be performed. Hence algorithms are presented for minimizing specification testing time. After specification testing time is minimized, the resulting test sets are supplemented with some simple, possibly non-specification, tests to achieve 100% fault coverage. Examples indicate that fault-driven test set development can lead to drastic reductions in production testing time.>

An algorithm for computing parametric yield is presented. The algorithm uses statistical modeling techniques and takes advantage of incremental knowledge of the problem to reduce significantly the number of simulations needed. Polynomial regression is used to construct simple equations mapping parameters to measurements. These simple polynomial equations can then replace circuit simulations in the Monte Carlo algorithm for computing parametric yield. The algorithm differs from previous statistical modeling algorithms using polynomial regression for three major reasons: first, the random error that is postulated in polynomial regression equations is taken into account when computing parametric yield; second, the variance of the yield is computed; and third, the algorithm is fully automated. Therefore a direct comparison with Monte Carlo methods can be made. Examples indicate that significant speed-ups can be attained over Monte Carlo methods for a large class of problems.>

Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage.>

The IC fabrication process contains several testing stages. Because of the high cost of packaging, the testing stage prior to aging, called wafer probe, is key in reducing the overall manufacturing cost. Typically in this stage, specification tests are performed. Even though specification tests can certainly distinguish a good circuit from all faulty ones, they are expensive, and many types of faulty behavior can be detected by simpler tests. The construction of a set of measurements that detects many faulty circuits before specification testing is described. Bounds on these measurements are specified, and an algorithm for test selection is presented. An example of a possible simple test is a test of DC voltages (i.e., parametric tests). This type of test is defined rigorously, and its effectiveness in detecting faulty circuits is evaluated.>

An efficient algorithm to determine the image of a parallelepiped under a linear transformation is presented. The work was motivated by certain problems in the testing of analog integrated circuits. The method is based on specifying the boundary hyperplanes that define the image polytope and is of polynomial complexity in n (the dimension of the parallelepiped), for a fixed value of the dimension of the range of the linear transformation. The algorithm has been implemented using library routines from LINPACK.