Characterizing the activating and inhibiting effect of protein-protein interactions (PPI) is fundamental to gain insight into the complex signaling system of a human cell. A plethora of methods has been suggested to infer PPI from data on a large scale, but none of them is able to characterize the effect of this interaction. Here, we present a novel computational development that employs mitotic phenotypes of a genome-wide RNAi knockdown screen and enables identifying the activating and inhibiting effects of PPIs. Exemplarily, we applied our technique to a knockdown screen of HeLa cells cultivated at standard conditions. Using a machine learning approach, we obtained high accuracy (82% AUC of the receiver operating characteristics) by cross-validation using 6,870 known activating and inhibiting PPIs as gold standard. We predicted de novo unknown activating and inhibiting effects for 1,954 PPIs in HeLa cells covering the ten major signaling pathways of the Kyoto Encyclopedia of Genes and Genomes, and made these predictions publicly available in a database. We finally demonstrate that the predicted effects can be used to cluster knockdown genes of similar biological processes in coherent subgroups. The characterization of the activating or inhibiting effect of individual PPIs opens up new perspectives for the interpretation of large datasets of PPIs and thus considerably increases the value of PPIs as an integrated resource for studying the detailed function of signaling pathways of the cellular system of interest.

Hardware failures occur especially due to external influences, component aging, or faulty interoperability. By testing, faulty components can be localized, allowing for fault isolation or repair. The contract testing strategy from software specifies component interoperability conditions, and systematically creates correspondent tests ensuring the operability of the system. We adapt contract testing to hardware, providing component specification, and monitoring thereof. Contract specification has to be specialized with requirements on the physical environment and component input signals. Contract testing is then executed through the monitoring of the contract parameters. Furthermore, to reason about the external cause of errors, signal faults are categorized. As a case study, we present an communication system. For this system, a contract is defined, and circuits implemented to perform contract testing and fault categorization. Communication faults, related to hardware errors and to sporadic environment disturbance, are injected in the developed system. These faults are completely detected, but can be only partially categorized by the monitoring approach.

In this paper we introduce a new object recognition method for detecting objects of arbitrary shapes based on a combination of the Fast Hough Transform (FHT) and the Dual-Point Generalized Hough Transform (DPGHT). We validate the proposed approach on medical images (cryosection, US, MRI) and describe its basic features. The proposed algorithm is robust, low memory consumptive and utilizes the advantages of the both FHT and DPGHT that makes it a good solution for medical object recognition applications.

In this work we present a prototype of a precise freehand 3D/4D ultrasound imaging system equipped with an universal wireless 3D tracker for digitizing spatial coordinates of an ultrasonic transducer, consider the system calibration using a plane phantom and carry out validation of the setup on a pig heart specimen. The system basic functionality, features and an application for cardiac purposes are described. Considering a number of visualization techniques used in the system, we demonstrate an alternative method of the surface reconstruction for sparse ultrasound data based on the active contour model.

The active buffer project is part of the CBM (compressed baryonic matter) experiment and takes advantage of the DPR (dynamic partial reconfiguration) technology, in which a dynamic module can be reconfigured while the static part and other dynamic modules keep running untouched. Due to DPR, design flexibility and simplicity are achieved at the same time. The correctness and the performance have been verified by multiple tests.

This paper presents a framework for rapid development of FPGA based custom processors based on floating-point calculation units. The framework consists of a fully parameterized floating-point library, an easy-to-use pipeline generator and an interface generator for memory and I/O-modules. The performance of this approach is shown for the implementation of an SPH-algorithm.

Different buffering strategies for communicating between custom computing machines and host computers are presented and compared. An approach that allows for the integration of diverse buffering schemes with arbitrary data conversion is presented and provides between 23% and 82% improvement when compared with separate operations.

In the last years, FPGAs became capable of performing complex floating-point based calculations. For many applications, highly parallel calculation units can be implemented which deliver a better performance than general-purpose processors. This paper focuses on applications where the calculations can be done in a pipeline, as it is often the case for simulations. A framework for rapid design of such calculation pipelines is described. The central part is a Perl based code generator, which automatically assembles floating-point operators into synthesizable hardware description code where the generator is directed by a pipeline description file. The framework is supplemented by various floating-point operators and support modules, which allow generating ready-to-use pipelines. The code generator dramatically reduces development time and produces high-quality results. The performance of the framework is demonstrated by the implementation of pipelines for gravitational forces and hydrodynamics

We develop the first approach Tor interactive volume visualization based on a sophisticated rendering method of shear-warp type, wavelet data encoding techniques, and a trivariate spline model, which has been introduced recently. As a first step of our algorithm, we apply standard wavelet expansions to represent and decimate the given gridded three-dimensional data. Based on this data encoding, we give a sophisticated version of the shear-warp based volume rendering method. Our new algorithm visits each voxel only once taking advantage of the particular data organization of octrees. In addition, the hierarchies of the data guide the local (re)construction of the quadratic super-spline models, which we apply as a pure visualization tool. The low total degree of the polynomial pieces allows to numerically approximate the volume rendering integral efficiently. Since the coefficients of the splines are almost immediately available from the given data, Bernstein-Bezier techniques can be fully employed in our algorithms. In this way, we demonstrate that these models can be successfully applied to full volume rendering of hierarchically organized data. Our computational results show that (even when hierarchical approximations are used) the new approach leads to almost artifact-free visualizations of high quality for complicated and noise-contaminated volume data sets, while the computational effort is considerable low, i.e. our current implementation yields 1-2 frames per second for parallel perspective rendering a 2563 volume data set (using simple opacity transfer functions) in a 5122 view-port.

In this paper we present a method that allows removing bony structures and calcifications from CT angiography (CTA) data. It relies on two data sets, one with (CA) and one without (NCA) contrast agent. In contrast to current approaches, the algorithm uses local rigid matching of each single object. Therefore, it allows compensating motion of the patient during acquisition. Furthermore, the method uses a highly accurate surface-matching procedure so that local mismatches can be as small as 3 voxels and therefore even arteries near the bone are mostly separated correctly. The overall system requires about 20 minutes on a Pentium 4 2.4 GHz with 1 GByte RAM for a 700 MByte data set (CA+NCA) and is currently used in the clinic for evaluation purposes.

This work investigates the suitability of using an FPGA coprocessor for speedup track finding algorithm for ATLAS Level 2 trigger. Two realizations of the same algorithm have been compared: C++ realization tested on a computer equipped with dual Xeon 2.4 GHz CPU, 64Bit/66MHz PCI bus, 1024 Mb DDR RAM main memories with Red Hat Linux 7.1; and hybrid C++ and VHDL realization tested on the same PC equipped in addition by MPRACE board (FPGA-Coprocessor board based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim). In the TRT-LUT algorithm, the most time consuming parts were implemented in VHDL and using the FPGA coprocessor. This realization can give us speed-up by factor ~2 for hybrid FPGA/CPU realization in comparison with CPU-only implementation.

3D interactive technologies become more and more applicable in nowadays medicine. Fast 3D reconstruction of CT-data is one of the examples. We present an acceleration of relevant reconstruction algorithms using FPGAs. For this purpose we used a board based on Xilinx Virtex II6000. Our system is able to reconstruct a 2563 voxel volume from 120 projections (5122j in 9s, using the filtered backprojection algorithm. In addition, it is shown how such a system is used to accelerate iterative algorithms, whereby the forward projection is performed by graphics hardware. The performance for iterative approaches is 4 min for SIRT (10 iterations) and 3 minutes for OS-EM (6 iterations) where the main limitation is the forward projection.

Abstract The design of PCR or DNA chip experiments is a time‐consuming process where bioinformatics is extensively used. The selection of the primers, which are immobilized on the DNA chip, requires a complex algorithm. Based on several parameters an optimized set of primers is automatically determined for a given gene sequence. This paper describes a parallel architecture which performs the optimization of the primer selection on a hardware accelerator. In contrast to the pure software approach, the parallel architecture gains a speedup of factor 500 using a PCI‐based hardware accelerator. This approach allows an optimization of a specified primer set in real time. Copyright © 2004 John Wiley & Sons, Ltd.

Abstract A collection of techniques is developed in this paper for ray casting free‐form deformed‐volume objects with high quality and efficiency. The known inverse ray deformation approach is combined with free‐form deformation to bend the rays to the opposite direction of the deformation, producing an image of the deformed volume without generating a really deformed intermediate volume. The local curvature is estimated and used for the adaptive selection of the length of polyline segments, which approximate the inversely deformed ray trajectories; thus longer polyline segments can be automatically selected in regions with small curvature, reducing deformation calculation without losing the spatial continuity of the simulated deformation. We developed an efficient method for the estimation of the local deformation function. The Jacobian of the local deformation function is used for adjustments of the opacity values and normal vectors computed from the original volume, guaranteeing that the deformed spatial structures are correctly rendered. The popular ray casting acceleration techniques, like early ray termination and space leaping, are incorporated into the deformation procedure, providing a speed‐up factor of 2.34–6.56 compared to the non‐optimized case. Copyright © 2003 John Wiley & Sons, Ltd.

This paper presents a high-performance FPGA solution to generic shape-based object detection in images. The underlying detection method involves representing the target object by binary templates containing positional and directional edge information. A particular scene image is preprocessed by edge segmentation, edge cleaning and distance transforms. Matching involves correlating the templates with the distance-transformed scene image and determining the locations where the mismatch is below a certain user-defined threshold. Although successful in the past, a significant drawback of these matching methods has been their large computational cost when implemented on a sequential general-purpose processor. In this paper we present a step by step implementation of the components of such object detection systems, taking advantage of the data and logical parallelism opportunities offered by an FPGA architecture. The realization of a pipelined calculation of the preprocessing and correlation on FPGA is presented in detail.

This paper investigates the usage of floating-point arithmetic on FPGAs for N-Body simulation in natural science. The common aspect of these applications is the simple computing structure where forces between a particle and its surrounding particles are summed up. The role of reduced precision arithmetic is discussed, and our implementation of a floating-point arithmetic library with parameterized operators is presented. On the base of this library, implementation strategies of complex arithmetic units are discussed. Finally the realization of a fully pipelined pressure force calculation unit consisting of 60 floating-point operators with a resulting performance of 3.9 Gflops on an off the shelf FPGA is presented.

This work extends RHCS with the capability to link to additional libraries at runtime just by specifying the libraries' filenames. The software components defined in the libraries are made available to the system by means of prototypes. By retaining the abstract interfaces from RHCS we are now able to dynamically compose a complete control framework at runtime without referring to any implementation of the components as building blocks. Also it is possible to extend and adapt the software at runtime according to the needs of reconfigured hardware, or even switch to emulation mode without recompiling the software. Additional components can be build and loaded independently of the existing runtime. This leads to the possibility to build the control software from a textual database describing the hardwares properties. Another possibility would be to use a graphical editor to compose the components to a running system. The performance overhead due to software indirection is monitored and the correctness of architecture is verified by implementing a functional prototype.

The aim of this project is to develop a new approach for the correction of bone deformities using a computer-aided surgery tool. We use measurement-based planning of corrections on CT data and an ultrasound-based navigation system for the real-time support of surgical operations. We implement a single-cut, close-and-open wedge osteotomy correction of complex 3D deformities. In the discussed method, virtual reality and image processing techniques allow planning and supporting of the operation on a personal computer. The designed software prototype significantly simplifies the process of osteotomy planning and allows surgeon training and assistance. The program reduces the total time of the operation planning and increases the accuracy of the correction significantly.

This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA1 and is embedded in a PCI plug-in card2 with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

In exploring the efficacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture enables exploration of the problems of implementing realistic multitasking.

High energy accelerator labs use huge detector systems to track particles. The ATLAS detector at CERN, Geneva (Switzerland), will provide complex three-dimensional images. A trigger system at the detector output is used to reduce the amount of data to a manageable size. Each trigger applies certain filter algorithms to select the very rare physically interesting events. The algorithm presented, processes data from a special detector called TRT, to generate a trigger decision within /spl ap/10 ms. System supervisors then decide together with other results whether the event will be rejected or passed to the next trigger level. Due to the restricted execution time for calculating the decision, fast pattern recognition algorithms are required. These algorithms require a high I/O bandwidth and high computing power. These reasons and the high degree of parallelism make it best suited for custom computing machines.

A web-based consulting system is described that is tailored for telepathology. It extends common services like remote image acquisition and web-transparent display by on image processing feature that is most critical in computer based pathology. The pathologist operates on a system that mirrors the workflow he/she is used to during examination. This makes the whole process understandable by non-computer scientists and allows for intuitive use. The whole system is realized using a three tier client-server architecture where the server hosts the image database and controls image handling and processing tasks. Clients are used for image acquisition and as a user-interface to the whole system. Since every client program is based on Java no specific requirements on the client side, except the availability of a Web-browser, are necessary.

No abstract available.

FPGA processors are very well suited for the implementation of image processing and pattern recognition tasks. This paper describes a particularly demanding application of this type and Enable++, the FPGA processor used. The system finds particle trades in high-energy physics detector images at a rate of 100 kHz. This requires to process a data stream of up to 500 MBytes/s in real time. The algorithm and the implementation on Enable++, a general purpose FPGA processor are described. Results from a software implementation are compared with the measurements from an implementation on the CCM. This implementation is 15 times faster than the software implementation on high end computers.

In the computing community field, programmable processors are going to fill the niche for special purpose computing devices. A typical example is ultra fast pattern recognition in experimental particle physics, a task for which we constructed two years ago (1993), Enable 1, an FPGA processor rather specialized for pattern recognition algorithms in /spl mu/s domain, but also provided with modest features for coping with more general applications. The paper presents the follow up model Enable++, a 2nd generation FPGA processor that offers several substantial enhancements over the previous system for a wider range of applications: Enable++ is structured into three different state of the art modules for providing computing power, flexible and high speed I/O communication and powerful intermodule communication with a raw bandwidth of 3.2 GByte/s by an active backplane. The technical realization of all three modules is guided by the maximum usage of field programmable logic. The actual demand of computing and I/O power can be satisfied by the number of modules plugged into the crate. Enhanced features of Enable++ comprise the configurable processor topology provided by programmable crossbar switches. In combination with the 4/spl times/4 FPGA array and 12 MByte distributed RAM, the Enable++ computing core offers a strongly increased and scalable computing power. For building new applications, the system offers a comfortable programming and debugging environment consisting of a compiler for the C like hardware description language spC, a simulator and a source level debugger for hardware design.

Abstract Volume rendering is a key technique in scientific visualization that lends itself to significant exploitable parallelism. The high computational demands of real‐time volume rendering and continued technological advances in the area of VLSl give impetus to the development of special‐purpose volume rendering architectures. This paper presents and characterizes three recently developed volume rendering engines which are based on the ray‐casting method. A taxonomy of the algorithmic variants of ray‐casting and details of each ray‐casting architecture are discussed. The paper then compares the machinefeatures and provides an outlook onfuture developments in the area of volume rendering hardware.

A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms and a speed-up factor of several orders of magnitude--including learning. The computational power is provided by a 2-dimensional systolic array of neural signal processors. Since the weights are stored outside these NSPs, memory size and processing power can be adapted individually to the application needs. A neural algorithms programming language, embedded in C(+2) has been defined for the user to cope with the neurocomputer. In a benchmark test, the prototype of SYNAPSE-1 was 8000 times as fast as a standard workstation.

A MIMD processor system is described, which allows forward and backward hardware error recovery (FHER and BHER) for data transfers. Fault-tolerant operation is provided by a multiple bus system and distributed error correction controller (ECC) hardware. Addresses and data are transferred through the bus system together with an error correction code, which is generated and checked by the ECC hardware. FHER is possible for all single-bit errors. Overlapping bus protocols allow these distributed ECC operations to be executed and synchronised concurrently with the transfer. Double-bit and multi-bit transfer errors as well as arbitration errors in the multiple bus system are detected and corrected by automatic rerouteing of the transfer path (BHER). These features improve the reliability of large multiprocessor systems significantly.

A general-purpose simulation system for neural networks is computationally very demanding. This paper presents some estimations of the computing power required, the necessary interconnection bandwidth, and the requisite memory size. Next, the hardware architecture of the NERV multiprocessor system is derived that fulfills these requirements. Up to 320 processors 68020 are used in a single VME crate together with a Macintosh II as a host computer. This set-up provides a computing power of 1300 MIPS together with a friendly graphical user interface. To support the simulation of arbitrarily interconnected networks and of asynchronous update models, the VME bus has been extended by a broadcast feature and a global max finder. The software architecture is outlined. It consists of system software, utilities, and application software.

A special bus structure, the SYNCBUS, is proposed, which supports task scheduling by hardware. It can be used efficiently in multiprocessor-(all processors identical) and polyprocessor-systems (different pools of processors) running real-time multitasking software with a dynamic load distribution. Tasks waiting for execution create prioritized interrupts, which are distributed over all available processors by hardware. An ``optimal'' load distribution, where the tasks of currently highest priority are assigned to the processors of each pool, is automatically set up and updated continually. The SYNCBUS operates independently of the pool sizes; increasing or decreasing the number of processors in case of changing system requirements or faults is possible. Its decentralized structure allows parallel and local handling of task queues and eliminates processor queues. Overhead times are cut down for three reasons: the faster operation of hardware compared to software table searches, avoidance of memory conflicts due to accessing common system tables by multiple processors, and avoidance of scheduling cycles which do not result in an actual reassignment of tasks to processors. A performance analysis using a mathematical model shows that overhead times can be reduced, depending on the system size and the frequency of task switches, by a factor of up to 102.