In this work, we provide a new software input mechanism using solely the smart phone gyroscope to detect taps made near the phone. Multiple experiments were conducted to determine the best conditions for enabling an interface that leverages taps made to a surface on which a device is placed. The experiments considered the impact of the phone type, the presence of a phone case, the surface type, and the sample rate. Taps made in eight different directions and at different distances ranging from on the side of the phone to 10 inches away from the phone were classified. The results motivated a keyboard layout that extends out from the smart phone, tripling the tapping area while still allowing full use of the smart phone touch screen. The successful classification of taps made on the prototype, called the keyboardless keyboard, opens a range of possibilities for an input interface which requires no hardware other than the smartphone's own gyroscope.

The Covid-19 pandemic accelerated the need for touchless interactions with technology in public spaces. By leveraging mobile phones which are equipped with Bluetooth wireless transmitters, we enable touchless and app-less interactions between people and technology. The Bluetooth signal broadcast from everyday devices such as smart phones is used by Bluetooth receivers, such as wireless earbuds, to pair the devices and communicate data. In this work, on the other hand, the broadcasted Bluetooth signal is detected, along with any change in the signal caused by rotating one's phone or waving one's hand by the phone. These intentional gestures with one's phone in the presence of an equipped Bluetooth receiver are interpreted as 'words' of a communication language. Without the need to pair devices or download any software, the communication language enables touchless interactions between a user holding a phone and a computing system in a public space

Sun and shade are two sides of the same coin. In this work we explore the use of the built-in light sensor in mobile devices to collect lux readings and extrapolate the presence or absence of shade along routes in communities. This work presents an end-to-end system for gathering lux readings, transferring the data to a cloud database, and detecting shaded regions. Detected shaded regions are visualized as a shade map to provide insightful to improve the coverage and distribution of shade.

This paper examines the challenges of using electrocardiogram (ECG) monitoring in wearable computing systems for addressing drowsiness detection while driving. The approaches for extrapolating a person's waking/sleeping state using time-series data is provided and verified against real ECG data available from the PhysioBank data archives. A system incorporating an off-the-shelf wearable ECG monitor and a prototype of a mobile application for carrying out the data analysis and computation is described.

This paper presents and evaluates approaches for synchronizing audio recordings in a system composed of mobile devices and cloud technologies. The proposed peak alignment approach, which uses a high decidable sound as a reference signal, is evaluated against an approach using a global clock made available by the cloud provider. Both approaches are evaluated with respect to variation and distance from the source sound and the size of the mobile device array.

Fluid retention, known medically as edema, is caused by the retention of fluid in the soft tissue of the lower extremities. This is most commonly found in the ankles and feet due to the effects of gravity. In this paper, we present a wearable device worn around the ankle that monitors edema in the legs and alerts the user of changes. We discuss the Edemeter system's physical and functional design. We also present results from several experiments characterizing the use of flex sensors for measuring ankle swelling, as well as system component power consumption and its impact on battery life.

Wearable computing is one of the fastest growing technology markets today, with smart watches poised to take over at least of half the wearable device market. Approaches to text entry on smart watches and other wrist worn systems, independent of the small screen, is of importance to the further growth of wearable systems. The consistent user interaction and hands-free, heads-up operation of smart watches paves the way for gesture recognition methods for text entry. This paper proposes a new text input method for smart watches, which utilizes motion sensor data and machine learning approaches to detect letters written in the air by a user. This method is less computationally intensive, less expensive, and unaffected by lighting factors, when compared to computer vision approaches. The AirDraw system prototype developed to test this approach is presented, along with experimental results with close to 71% accuracy in letter recognition.

This paper describes a variety of side-channel attacks on mobile and wearable computing systems, exposing vulnerabilities in their system and software architectures. Specifically addressed are malware approaches that passively leverage sensors on-board the systems to monitor user information for sensitive information retrieval. Some potential countermeasures at the system and user interface level are provided.

This paper investigates and addresses the vulnerabilities of existing physical unclonable functions (PUFs). We first develop a PUF reverse engineering approach by conducting gate-level characterization (GLC). Based on the gate-level delay properties, we emulate the target PUF by designing a functionally equivalent PUF replication. Furthermore, in order to prevent such an attack, we develop a new sequential PUF architecture that is resilient to side channel-based reverse engineering. We obtain accurate results in emulating the timing behavior of the existing arbiter-based PUFs. Also, the randomness obtained from the sequential PUFs is significantly higher compared to the existing PUFs.

Hardware metering, the extraction of unique and persistent identifiers (IDs), is a crucial process for numerous integrated circuit (IC) intellectual property protection tasks. The currently known hardware metering approaches, however, are subject to alternations due to device aging, since they employ unstable manifestational IC properties. We, on the other hand, have developed the first robust hardware metering approach by using physical-level gate proprieties for ID generation. By using effective channel length, which is resilient to aging, and threshold voltage, which is essentially independent across gates and suitable for calculating the uniqueness of the IDs, we overcome the limitations of the existing approaches. Also, despite the increase in threshold voltage that occurs with aging, the original threshold voltage value can be extracted through intentional IC aging. Our ID generation procedure first employs two types of side channels, namely switching power and leakage power, to extract metering results for each gate. Next, we show that localized delay measurements alone are sufficient for accurate characterization of large sets of gates. Finally, by using threshold voltage for ID creation, we are able to obtain low probabilities of coincidence between legitimate and pirated ICs. The application of the approach to a set of benchmarks quantitatively establishes the effectiveness of the new hardware metering approach.

In this paper, we present a mechanism for estimating data quality of BANs composed of cardiac sensors. Currently available cardiac monitoring sensors suffer from high level of noise generated from loose physical contact of the sensor node due to the highly mobile and pervasive environment of the BAN (e.g., at-home remote health care applications). Therefore, there is a need to estimate the data quality of individual cardiac sensors as well as the data quality of the overall BAN while particularly considering the resource scarceness of BAN-scale mobile systems. The proposed method successfully estimates the data quality of a BAN without employing computationally expensive machine learning techniques. It also provides a number of resource management options that enable efficient data quality estimation. We present experimental results of four participants with three off-the-shelf cardiac sensors to form a BAN. We also present simulation results to examine if the proposed mechanism can successfully detect health hazardous events such as heart arrhythmia.

No abstract available.

Modern hardware security has a very broad scope ranging from digital rights management to the detection of ghost circuitry. These and many other security tasks are greatly hindered by process variation, which makes each integrated circuit (IC) unique, and device aging, which evolves the IC throughout its lifetime. We have developed a singular value decomposition (SVD)-based procedure for gate-level characterization (GLC) that calculates changes in properties, such as delay and switching power of each gate of an IC, accounting for process variation and device aging. We employ our SVD-based GLC approach for the development of two security applications: hardware metering and ghost circuitry (GC) detection. We present the first robust and low-cost hardware metering scheme, using an overlapping IC partitioning approach that enables rapid and scalable treatment. We also map the GC detection problem into an equivalent task of GLC consistency checking using the same overlapping partitioning. The effectiveness of the approaches is evaluated using the ISCAS85, ISCAS89, and ITC99 benchmarks. In hardware metering, we are able to obtain probabilities of coincidence in the magnitude of 10-8or less, and we obtain zero false positives and zero false negatives in GC detection.

We have developed an ultra low power (well below 1 nano-joule per transaction), ultra high speed (less than 1 nanosecond), and low cost (a few hundred gates) public physically unclonable function (PPUF). We have also developed the first PPUF-based smart card (SC). We analyze and demonstrate the security of this new SC against several families of potential security attacks.

Current hardware metering techniques, which use manifestational properties of gates for ID extraction, are weakened by the non-uniform effects of aging in conjunction with variations in temperature and supply voltage. As an integrated circuit (IC) ages, the manifestational properties of the gates change, and thus the ID used for hardware metering can not be valid over time. Additionally, the previous approaches require large amounts of costly measurements and often are difficult to scale to large designs. We resolve the deleterious effects of aging by going to the physical level and primarily targeting the characterization of threshold voltage. Although threshold voltage is modified with aging, we can recover its original value for use as the IC identifier. Another key aspect of our approach involves using IC segmentation for gate-level characterization. This results in a cost effective approach by limiting measurements, and has a significant effect on the approach scalability. Finally, by using threshold voltage for ID creation, we are able to quantify the probability of coincidence between legitimate and pirated ICs, thus for the first time quantitatively and accurately demonstrating the effectiveness of a hardware metering approach.

Heart failure is a leading cause of death in the United States, with around 5 million Americans currently suffering from congestive heart failure. The WANDA B. wireless health technology leverages sensor technology and wireless communication to monitor heart failure patient activity and to provide tailored guidance. Patients who have cardiovascular system disorders can measure their weight, blood pressure, activity levels, and other vital signs in a real-time automated fashion. The system was developed in conjunction with the UCLA Nursing School and the UCLA Wireless Health Institute for use on actual patients. It is currently in use with real patients in a clinical trial.

Hardware Trojan horses (HTHs) are the malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. There are numerous HTHs sources including untrusted foundries, synthesis tools and libraries, testing and verification tools, and configuration scripts. HTH attacks can greatly comprise security and privacy of hardware users either directly or through interaction with pertinent systems and application software or with data. However, while there has been a huge research and development effort for detecting software Trojan horses, surprisingly, HTHs are rarely addressed. HTH detection is a particularly difficult task in modern and pending deep submicron technologies due to intrinsic manufacturing variability.

This article presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. The driver application that we present is a medical jacket, which requires an extremely high level of robustness and fault tolerance. The power consumption of such jacket is another key technological constraint. Our proposed interconnection network is a mesh of wires. A jacket made of fabric and wires would be susceptible to accidental damage via tears. By modeling the tears, we evaluate the probability of having failures on every segment of wires in our mesh interconnection network. Then, we study two problems of placement and routing in the sensor networks such that the fault tolerance is maximized while the power consumption is minimized. We develop efficient integer linear programming (ILP) formulations to address these problems and perform both placement and routing, simultaneously. This ensures that the solution is a lower bound for both problems. We evaluate the effectiveness of our proposed techniques on a variety of benchmarks.

Dynamic reconfiguration imposes significant penalties in terms of performance and energy. Scheduling the execution of tasks on a dynamically reconfigurable device is therefore of critical importance. Likewise, other application domains have cost models that are effectively the same as dynamic reconfiguration; examples include: data transmission across multiprocessor systems; dynamic code updating and reprogramming of motes in sensor networks; and module allocation, wherein the sharing of resources effectively eliminates inherent reconfiguration costs. This article contributes a fully polynomial time approximation algorithm for the problem of scheduling independent tasks onto a fixed number of heterogeneous reconfigurable resources, where each task has a different hardware and software latency on each device; the reconfiguration latencies can also vary between resources. A general-purpose processor and a field programmable gate array were used to experimentally validate the proposed technique using a pair of encryption algorithms. The latencies of the schedules obtained by the approximation scheme were at most 1.1× longer than the optimal solution, which was found using integer linear programming; this result is better than the theoretical worst-case guarantee of the approximation algorithm, which was 1.999×. The length of the schedules obtained using list scheduling, a well-known polynomial time heuristic, were at most 2.6× longer than optimal.

Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft-error rates caused by single-event upsets (SEUs) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a nonlinear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit. We prove that it is sufficient to consider a linear number of constraints. 4) We generalize our methodology to include nonlinear delay models and leakage power as well. As an important preprocessing step, we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. Furthermore, we adapt our method to incorporate process variation and evaluate our gate sizing technique under uncertainty. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100%-200% while, on average, the power reduction is simultaneously decreased by less than 6%-10%, respectively, compared to the optimal power saving with no error rate constraints.

In highly power constrained sensor networks, harvesting energy from the environment makes prolonged or even perpetual execution feasible. In such energy harvesting systems, energy sources are characterized as being regenerative. Regenerative energy sources fundamentally change the problem of power scheduling for embedded devices. Instead of the problem being one of maximizing the lifetime of the system given a total amount of energy, as in traditional battery powered devices, the problem becomes one of preventing energy depletion at any given time. Coupling relatively computationally intensive applications, such as video processing applications, with the constrained FPGAs that are feasible on power constrained embedded systems, makes dynamic reconfiguration essential. It provides the speed comparable to a hardware implementation, but it also allows the dynamic reconfiguration to meet the multiple application needs of the system. Different applications can be loaded on the FPGA, as the system's needs change over time. The problem becomes how to schedule the dynamic reconfiguration to appropriately make use of the regenerative energy source, to ensure the proper availability of energy for the system over time. This paper presents a methodology for carrying out dynamic reconfiguration for regenerative energy sources, based on statistical analysis of tasks and supply energy. The approach is evaluated through extensive simulations. Additionally, the implementation has been evaluated on regenerative energy, dynamically reconfigurable prototype, known as the MicrelEye. The approach is shown to miss 57.7% less deadlines on average than the current approach for reconfiguration with regenerative energy sources

Light-weight embedded systems are now gaining more popularity due to the recent technological advances in fabrication that have resulted in more powerful tiny processors with greater communication capabilities that pose various scientific challenges for researchers. Perhaps the most significant challenge is the energy consumption concern and reliability, mainly due to the small size of batteries. In this tutorial, we portray a brief description of low-power, light-weight embedded systems, depict several power profiling studies previously conducted, and present several research challenges that require low-power consumption in embedded systems. For each challenge, we highlight how low-power designs may enhance the overall performance of the system. Finally, we present a several techniques that minimize the power consumption in such systems.

Dictionary compression mechanisms identify redundant sequences of instructions that occur in a program. The sequences are extracted and copied to a dictionary. Each sequence is then replaced with a codeword that acts as an index into the dictionary, thereby enabling decompression of the program at runtime. The problem of optimally organizing a dictionary consisting solely of redundant sequences in order to maximize compression has long been known to be NP-Complete [23]. This paper addresses the problem of dictionary construction when redundant code fragments are represented as Data Flow Graphs (DFGs) rather than linear sequences of instructions. Since there are generally multiple legal schedules for a given DFG G, a compiler must determine a schedule for G so that other DFGs that are subgraphs of G can reference some substring of G’s final code sequence. This reduces the size of the dictionary, and in turn, the size of the compressed program. Our experiments with 10 MediaBench [18] applications yielded reductions in dictionary size ranging from 21.14 % to 29.76 % compared to a naïve approach.

Reconfiguration delay is one of the major barriers in the way of dynamically adapting a system to its application requirements. The run-time reconfiguration delay is quite comparable to the application latency for many classes of applications and might even dominate the application run-time. In this paper, we present an efficient optimal algorithm for minimizing the run-time reconfiguration (context switching) delay of executing an application on a dynamically adaptable system. The system is composed of a number of cameras with embedded reconfigurable resources collaborating in order to track an object. The operations required to execute in order to track the object are revealed to the system at run-time and can change according to a number of parameters, such as the target shape and proximity. Similarly, we can assume that the applications comprising tasks are already scheduled and each of them has to be realized on the reconfigurable fabric in order to be executed.The modeling and the algorithm are both applicable to partially reconfigurable platforms as well as multi-FPGA systems. The algorithm can be directly applied to minimize the application run-time for the typical classes of applications, where the actual execution delay of the basic operations is negligible compared to the reconfiguration delay. We prove the optimality and the efficiency of our algorithm. We report the experimental results, which demonstrate a 2.5--40% improvement on the total run-time reconfiguration delay as compared to other heuristics.