Currently, multimodel databases are widely used in modern applications, but the default configuration often fails to achieve the best performance. How to efficiently manage and tune the performance of multimodel databases is still a problem. Therefore, in this study, we present a configuration parameter tuning tool MMDTune+ for ArangoDB. First, the selection of configuration parameters is based on the random forest algorithm for feature selection. Second, a workload‐aware mechanism is based on k‐means++ and the Pearson correlation coefficient to detect workload changes and match the empirical knowledge of historically similar workloads. Finally, the ArangoDB configuration parameters are optimized based on the improved TD3 algorithm. The experimental results show that MMDTune+ can recommend higher‐quality configuration parameters for ArangoDB compared to OtterTune and CDBTune in different scenarios.

As the need for handling data from various sources becomes crucial for making optimal decisions, managing multi-model data has become a key area of research. Currently, it is challenging to strike a balance between two methods: polyglot persistence and multi-model databases. Moreover, existing studies suggest that current benchmarks are not completely suitable for comparing these two methods, whether in terms of test datasets, workloads, or metrics. To address this issue, the authors introduce MDBench, an end-to-end benchmark tool. Based on the multi-model dataset and proposed workloads, the experiments reveal that ArangoDB is superior at insertion operations of graph data, while the polyglot persistence instance is better at handling the deletion operations of document data. When it comes to multi-thread and associated queries to multiple tables, the polyglot persistence outperforms ArangoDB in both execution time and resource usage. However, ArangoDB has the edge over MongoDB and Neo4j regarding reliability and availability.

Abstract As we all know, the performance of database management system is directly linked to a vast array of knobs, which control various aspects of system operation, ranging from memory and thread counts settings to I/O optimization. Improper settings of configuration parameters are shown to have detrimental effects on performance, reliability and availability of the overall database management system. This is also true for multi-model databases, which use a single platform to support multiple data models. Existing approaches for automatic DBMS knobs tuning are not directly applicable to multi-model databases due to the diversity of multi-model database instances and workloads. Firstly, in cloud environment, they have difficulty adapting to changing environments and diverse workloads. Secondly, they rely on large-scale high-quality training samples that are difficult to obtain. Finally, they focus primarily on throughput metrics, ignoring tuning requirements for resource utilization. Therefore, in this paper, we propose a multi-model database configuration parameters tuning solution named MMDTune. It selects influential parameters, recommends the optimal configurations in a high-dimensional continuous space. For different workloads, the TD3 algorithm is improved to generate reasonable parameter adjustment plans according to the internal state of the multi-model databases. We conduct extensive experiments under 5 different workloads on real cloud databases to evaluate MMDTune. Experimental results show that MMDTune adapts well to a new hardware environment or workloads, and significantly outperforms the representative tuning tools, such as OtterTune, CDBTune.

Aiming at the shortcomings of the current YOLOv3 model, such as large size, slow response speed, and difficulty in deploying to real devices, this paper reconstructs the target detection model YOLOv3, and proposes a new lightweight target detection network YOLOv3-promote: Firstly, the G-Module combined with the Depth-Wise convolution is used to construct the backbone network of the entire model, and the attention mechanism is introduced and added to perform weighting operations on each channel to get more key features and remove redundant features, thereby strengthening the identification ability of feature network model’s to distinguish target objects among background; Secondly, in order to delete some less important channels to achieve the effect of compressing the model size and improving the calculation speed, the size of the scaling factor gamma in the batch normalization layer is used; Finally, based on NVIDIA’s TensorRT framework model conversion and half-precision acceleration were carried out, and the accelerated model was successfully deployed on the embedded platform Jetson Nano. The performed KITTI experimental results show that the inference speed of our proposed method is about 5 times that of the original model, the parameter volume is reduced to one tenth, the mAP is increased from 86.1% of the original model to 93.1%, and the FPS reaches 25.5fps, realizing the requirements of real-time detection with high precision.

The smart ocean has aroused the interest of government, business, and academia because of the wealth of marine resources. It has been suggested to use underwater Internet of Things (IoT) frameworks to collect a variety of data from smart seas that can aid in the underwater green transport system, ecological sustainability, military intelligence gathering, and a variety of other operations. Because of the limited resources accessible to IoT devices regarding communication overhead, processing expenses, and battery capacity, security and privacy concerns in underwater green transport systems have lately been a critical source of worry. In this context, We presented a unique identity-based authentication mechanism for underwater green transport systems. Our suggested solution uses lightweight authentication mechanisms that prove secure communication between different elements of the green transport system.

Summary Outsourcing data to cloud servers is a popular service for data owners, however, how to check the integrity and freshness of the outsourced data is very challenge. Recently, Jin et al. proposed a cloud auditing protocol with full integrity and freshness support for cloud data, unfortunately in this article, we show their proposal is not secure. Concretely, the cloud servers can forge the authentication tag and thus has the ability to forge proof of data possession, which obviously invalidates their cloud auditing protocol. We also give a new cloud auditing protocol and analysis its security and performance. The results show our protocol is more efficient and secure.

The hunt for increased reliability in systems for critical applications is a never-ending process and is a point of concern for designers in several different fields, such as nuclear reactors. This concern becomes more prominent when a new device technology is integrated into the options for the development of those systems, such as programmable logic devices like the FPGA. With the constant breakthroughs in this technology, there has been an increase in the capacity and the performance of FPGAs. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. This work proposes a resilient and adaptable hardware architecture that increases the reliability of circuits implemented in FPGAs, based on a classic active redundancy model, Triple Modular Redundancy with spares. Also, it brings forth a novel hardware architecture that can easily be ported to different FPGA models without compromising performance, reliability, and availability. We discuss and analyze these requirements for the proposed architecture and show that it is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area.

Particle swarm optimization (PSO) is an evolutionary heuristics-based method used for continuous function optimization. Compared with existing stochastic methods, PSO is very robust. Nevertheless, for real-world optimizations, it requires a high computational effort. In general, parallel implementations of PSO provide better performance. However, this depends heavily on the parallelization strategy engineered as well as the number and characteristics of the exploited processors. In this paper, we analyze three different parallelization strategies: a Particle-oriented Strategy (PoS); a Dimension-oriented Strategy (DoS) and a Cooperation-oriented Strategy (CoS). PoS parallelizes the particle's work. DoS focuses on the work done with respect to each of the problem dimensions and does it in parallel. CoS subdivides the optimization problem into many simpler subproblems, each of which focuses on a distinct subset of the original problem dimensions. The optimization work for all the yielded subproblems is done in parallel. Note that in the second and third strategies, all particles act in parallel too. We map the three strategies onto a Graphics Processing Units (GPU)-based architecture. The performance of the implementations is evaluated using four benchmark functions, considering high-dimension instances. We compare the speedups achieved by the GPU-based implementations of the considered parallelization strategies to the reference sequential PSO implementation as well as to existing PSO implementation on Graphics Processing Units.

Custom Instruction Identification is an important part in the design of efficient Application-Specific Processors (ASIPs). It consists of profiling of a given application to find patterns of basic operations that are frequently executed. Operations of such patterns can be implemented together as a single custom instruction to speedup the execution of the application. Because of the problem's high complexity, several methods have been proposed for specific single-issue (RISC) processors and architectures, limiting the shape and size of custom instructions that can actually be identified and, possibly, implemented. In this paper, we propose and discuss an efficient custom instruction set identification method and corresponding automatic tool for multi-issue VLIW ASIPs, which search for the common operation patterns of the most frequently executed basic blocks of a given application, with different sizes and shapes. The speedup results for the custom instructions identified by our tool are provided for a set of benchmark applications. The speedup is up to 68%, with only a few custom instructions used.

introduction Share on Introduction to the special section on self-adaptive systems: Models and algorithms Authors: Abdelhamid Bouchachia Bournemouth University, UK Bournemouth University, UKView Profile , Nadia Nedjah State University of Rio de Janeiro, Brazil State University of Rio de Janeiro, BrazilView Profile Authors Info & Claims ACM Transactions on Autonomous and Adaptive SystemsVolume 7Issue 1April 2012 Article No.: 13pp 1–4https://doi.org/10.1145/2168260.2168273Published:04 May 2012Publication History 3citation330DownloadsMetricsTotal Citations3Total Downloads330Last 12 Months8Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this paper, we use two multi-objective evolutionay algorithms to address the problem of selecting the most adequate set of IPs (from an available library) that best implements the application. The IP selection optimization is driven by the minimization of hardware area, total execution time and power consumption.

In this paper, we propose an architecture, which we call GridRT, capable of dealing with the main features, such as shadows and reflections effects, of Ray Tracing used for rendering three-dimensional scenes. This architecture achieves an efficient overall performance yet using a simple and compact massively parallel design. The design exploits the usage of Xilinx®Floating Point Operator IP Core and the spatial data structure of Regular Grids.

Modular exponentiation is an important operation in several public-key cryptosystems. It is performed using successive modular multiplications. For the sake of efficiency, one needs to reduce the total number of required modular multiplications. In this paper, we propose an efficient hardware implementation for computing modular exponentiations using the the concept of addition chain. This implementation use an addition chain tailored for the exponent to compute the modular power and evolved by a genetic algorithm. The system-on-chip (SoC) methodology is used to yield a hardware/software co-design of the modular exponentiation that takes advantage of the evolved addition chain. We provide a comparison of the proposed implementation to three existing ones using the performance factor, which takes into account both space and time requirements.

Modular exponentiation is a basic operation in cryptosystems. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. The efficiency of the modular exponentiation, in turn, depends mainly on that of modular multiplications as the former is somehow a repetition of the latter. One of the methods that computes the modular power is the sliding-window method, which pre-processes the exponent intozeroandnon-zeropartitions.Zeropartitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel system-on-chip (SoC) implementation for computing modular exponentiation using the sliding-window method. We also propose a hardware-only implementation for that operation. The partitioning strategy used in both approaches allows constant-length non-zero partitions, which increases the average number ofzeropartitions and so decreases that of non-zero partitions. The partitioning strategy allows variable-lengthzeropartitions. The hardware/software co-design implements the modular multiplication on hardware and the rest of the system in software. We provide a useful comparison of the SoC-based implementation against hardware-only implementation. Both of the proposed implementations can be used in any industrial embedded system that needs to secure the handled information.

Modular exponentiation is a basic operation in various applications, such as cryptography. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers devoted special interest to providing smart methods and efficient implementations for modular exponentiation. One of these methods is the sliding-window method, which pre-processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel hardware for computing modular exponentiation using the slidingwindow method. The partitioning strategy used here allows variable-length non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. The implementation is efficient when compared against related existing hardware implementations.

In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This is design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Finally, we compare the proposed hardware and existing ones.

Genetic programming is used as an alternative methodology to automatically generate secure and minimal hardware designs of public-key cryptosystems such as RSA encryption system. We evolve optimal hardware circuits for modular exponentiation, which a cornerstone operation in almost every cryptographic system. The evolved circuits minimize both space (f.e. required gate number) and time (i.e. encryption and decryption time). The evolved designs are shielded against side-channel leakage and hence secure. The structure of the cryptographic circuit is random and so the private key cannot be deduced using known attacks. We compare our results against existing well-known designs, which were produced by human designers based on the binary method.

Modular exponentiation is a cornerstone operation to several public-key cryptosystems. It is performed using successive modular multiplications. This operation is time consuming for large operands, which is always the case in cryptography. For software or hardware fast cryptosystems, one needs thus to reduce the total number of modular multiplication required. Existing methods attempt to reduce this number by partitioning the exponent in constant or variable size windows. In this paper, we propose a fast and compact reconfigurable hardware for computing modular exponentiation using the m-ary method. The cryptographic hardware is low-cost and concise and therefore can be embedded in almost all electronic devices that use encrypted data.

In this paper, we propose reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. This is used to build a feed-forward artificial neural network. For this purpose, we use field-programmable gate arrays, i.e. FPGAs. However, as the state-of-the-art FPGAs still lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement the computation performed by a neuron. The multiplication and addition of stochastic values is simply implemented by an ensemble of XNOR and AND gates respectively.

Modular exponentiation is the cornerstone computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. We describe the characteristics of three architectures designed to implement modular exponentiation using the fast binary method: the first FPGA prototype has a sequential architecture, the second has a parallel architecture and the third has a systolic array-based architecture. We compare the three prototypes using the time/spl times/area classic factor. All three prototypes implement the modular multiplication using the popular Montgomery algorithm.

Modular exponentiation and modular multiplication are the cornerstone computations performed in public-key cryptography systems such as RSA cryptosystem. The operations are time consuming for large operands. Much research effort is directed towards an efficient hardware implementation of both operations. This paper describes the characteristics of two architectures: the first one implements modular multiplication using a systolic version of the fast Montgomery algorithm and the other to implement the parallel binary exponentiation algorithm. The latter uses two Montgomery modular multipliers. Results in terms of space and time requirements for an FPGA prototype are given.

We propose a practical technique to compile left-to-right pattern-matching of prioritised overlapping function definitions in equational languages to a matching automaton from which efficient code can be derived. First, a matching table is constructed using a compilation method similar to the technique that YACC employs to generate parsing tables. The matching table obtained allows for the pattern-matching process to be performed without any backtracking. Then, the known information about right sides of the equations is inserted in the matching table in order to speed-up the pattern-matching process. Most of the discussion assumes that the processed pattern set is left-linear, the non-linear case being handled by an additional pass following the matching stage. Copyright © 1999 John Wiley & Sons, Ltd.