Toolglass™ widgets are new user interface tools that can appear, as though on a transparent sheet of glass, between an application and a traditional cursor.They can be positioned with one hand while the other positions the cursor.The widgets provide a rich and concise vocabulary for operating on application objects.These widgets may incorporate visual filters, called Magic Lens™ filters, that modify the presentation of application objects to reveal hidden information, to enhance data of interest, or to suppress distracting information.Together, these tools form a see-through interface that offers many advantages over traditional controls.They provide a new style of interaction that better exploits the user's everyday skills.They can reduce steps, cursor motion, and errors.Many widgets can be provided in a user interface, by designers and by users, without requiring dedicated screen space.In addition, lenses provide rich context-dependent feedback and the ability to view details and context simultaneously.Our widgets and lenses can be combined to form operation and viewing macros, and can be used over multiple applications.

This paper describes the Liveboard, a large interactive display system. With nearly one million pixels and an accurate, multi-state, cordless pen, the Liveboard provides a basis for research on user interfaces for group meetings, presentations and remote collaboration. We describe the underlying hardware and software of the Liveboard, along with several software applications that have been developed. In describing the system, we point out the design rationale that was used to make various choices. We present the results of an informal survey of Liveboard users, and describe some of the improvements that have been made in response to user feedback. We conclude with several general observations about the use of large public interactive displays.

specification of a high·performance successor to the Alto personal minicomputer, in use since 1973. After four years, the resulting machine, called the Dorado, was in use within the research community at PARCo This paper begins with an overview of the design goals, archi-tecture, and implementation of the Dorado and then provides a retrospective view and critique of the Dorado project as a whole. The major machine architectural features are evaluated, other project aspects such as design automation and management structures are explained, a chronological history with milestones is included, and a variety of accomplish· ments, red herrings, and shortfalls is discussed. The paper concludes with some specula-tions on what the project might have done differently and what might be done differently today instead of in the late 1970s. Although more than a dozen scientists and technicians contributed to the project, the

The memory system of the Dorado, a compact high- performance personal computer, has very high I/O bandwidth, a large paged virtual memory, a cache, and heavily pipelined control; this paper discusses all of these in detail. Relatively low-speed I/O devices transfer single words to or from the cache; fast devices, such as a color video display, transfer directly to or from main storage while the processor uses the cache. Virtual addresses are used in the cache and for all I/O transfers. The memory is controlled by a seven-stage pipeline, which can deliver a peak main-storage bandwidth of 533 million bits/s to service fast I/O devices and cache misses. Interesting problems of synchronization and scheduling in this pipeline are discussed. The paper concludes with some performance measurements that show, among other things, that the cache hit rate is over 99 percent.

This paper describes the design goals, micro- architecture, and implementation of the microprogrammed processor for a compact high performance personal computer. This computer supports a range of high level language environments and high bandwidth I/O devices. Besides the processor, it has a cache, a memory map, main storage, and an instruction fetch unit; these are described in other papers. The processor can be shared among 16 microcoded tasks, performing microcode context switches on demand with essentially no overhead. Conditional branches are done without any lookahead or delay. Microinstructions are fairly tightly encoded, and use an interesting variant on control field sharing. The processor implements a large number of internal registers, hardware stacks, a cyclic shifter/masker, and an arithmetic/logic unit, together with external data paths for instruction fetching, memory interface, and I/O, in a compact, pipe-lined organization.