We present a dynamic dataflow execution model, called the aggregated hierarchical abstract hardware architecture (or AHAHA), for use in FPGA based applications. High level language implementations targetting FPGAs use either handshaking or control-path solutions to schedule computations. Among the handshaking variety are the Compaan VHDL Visitor; the control-path solution uses a simplified form of handshaking which operates only in the same direction as the data flows and is used for example in MAP-C.

The authors have described a method of testing various implementations of co-designs generated by the SA-C compiler. Each form can be examined using co-simulation. The host code is able to communicate with a FPGA board simulated in ModelSim as if it were physical hardware. The co-simulation approach briefly described in this paper allows us to test and analyze all parts of the complete co-design. In essence, the compiler is able to perform automated co-verification for any SA-C program. At the highest level of simulation, it allows functional verification of the VHDL generated by the compiler. At the lowest level of detail, the FPGA simulation is phase accurate and mimics the hardware behavior down to the individual configurable logic block

The prevalence of software reference code motivates investigation into efficient implementations of software architectures on field-programmable devices. Modern FPGAs allow designers to generate multi-processor architectures that exactly match the processing needs of the algorithm. This paper describes an architecture supporting the single program multiple data model of parallel processing, and presents results taken from a parallel implementation of the JPEG2000 encoding algorithm and Mandelbrot set generation.

This paper deals with the evaluation of FIFO for connecting custom cores to processors in FPGA. Two case studies were done in order to evaluate the use of FIFO in the context of hardware-software co-design. One case study analyzes the rendering images of the Mandelbrot set and the other one deals with the game of Connect Four. In both applications a simple co-processor provides the most speed-up, where a higher quality co-processor implementation was exhibited.

The Cameron project has developed a language called single assignment C (SA-C), and a compiler for mapping image-based applications written in SA-C to field programmable gate arrays (FPGAs). The paper tests this technology by implementing several applications in SA-C and compiling them to an Annapolis Microsystems (AMS) WildStar board with a Xilinx XV2000E FPGA. The performance of these applications on the FPGA is compared to the performance of the same applications written in assembly code or C for an 800 MHz Pentium III. (Although no comparison across processors is perfect, these chips were the first of their respective classes fabricated at 0.18 microns, and are therefore of comparable ages.) We find that applications written in SA-C and compiled to FPGAs are between 8 and 800 times faster than the equivalent program run on the Pentium III.

This paper describes the implementation of an automatic target recognition (ATR) Probing algorithm on a reconfigurable system, using the SA-C programming language and optimizing compiler. The reconfigurable system is 800 times faster than a comparable Pentium running a C implementation of the same probing task. The reasons for this are analyzed.

We describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into dataflow graphs and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces dataflow graphs and a dataflow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application programmer.

Velocity Picking is the problem of picking velocity-time pairs based on a coherence metric between multiple seismic signals. Coherence as a function of velocity and time can be expressed as a 2-D color semblance velocity image. Currently, humans pick velocities by looking at the semblance velocity image; this process can take days or even weeks to complete for a seismic survey. The problem can be posed as a geometric feature matching problem. A feature extraction algorithm can recognize islands (peaks) of maximal semblance in the semblance velocity image: a heuristic combinatorial matching process can then be used to find a subset of peaks which maximizes the coherence metric. The peaks define a polyline through the image, and coherence is measured in terms of the summed velocity under the polyline and the smoothness of the polyline. Our best algorithm includes a constraint favoring solution near the median solution for the local area under consideration. Each image is first processed independently. Then, a second pass of optimization includes proximity to the median as an additional optimization criterion. Our results are similar to those produced by human experts.