The 55th Design Automation Conference (DAC) held its first System Design Contest (SDC) in 2018. SDC'18 features a lower power object detection challenge (LPODC) on designing and implementing novel algorithms based object detection in images taken from unmanned aerial vehicles (UAV). The dataset includes 95 categories and 150k images, and the hardware platforms include Nvidia's TX2 and Xilinx's PYNQ Z1. DAC-SDC'18 attracted more than 110 entries from 12 countries. This paper presents in detail the dataset and evaluation procedure. It further discusses the methods developed by some of the entries as well as representative results. The paper concludes with directions for future improvements.

The Convolutional Neural Network (CNN) is a breakthrough technique in object classification and pattern recognition. It has enabled computers to achieve performance superior to humans in specialized image recognition tasks. Prior art CNNs learn object features by stacking multiple convolutional/non-linear layers in sequence on top of a classifier. In this work, we propose a Hierarchical CNN (HCNN) which is inspired by a coarse-to-fine human learning methodology. For a given dataset, we introduce a CNN-oriented clustering algorithm to separate classes into K subsets, which are referred to as families. Then, the HCNN algorithm trains K+1 classification CNNs: one CNN for family classification and K dedicated CNNs corresponding to each family for member classification. We evaluate this HCNN approach on the German Traffic Sign Recognition Benchmark (GTSRB), and achieve 99.67% correct detection rate (CDR), which is superior to the best reported results (99.46%) achieved by a single network.

The DAC community will have an opportunity to offer its perspective and thoughts on the political landscape in the United States. With election season in full swing, the country is about to elect a new administration that could be from a new party.

Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to multiprocessor platforms as a vehicle for their realization. But entirely fixed platforms composed of entirely fixed components lack the flexibility and ability to be optimized to the application to offer the best solution in any of these areas. Configurability at multiple levels offers a much better chance to optimize the resulting multiprocessor platform. Existing and emerging technologies for configurable and extensible processors and the creation of configurable multiprocessor subsystem platforms offer significant capability to design teams to both differentiate and optimize their products.

Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors. This energy advantage comes from three improvements. First, configuration of the instruction set permits a much closer fit of the processor to the target applications, reducing the number of execution cycles required. Second, configuring the processor removes unneeded features, reducing power and area overhead. Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation. The first improvement has been well-studied. Analysis of the second and third improvements requires detailed circuit and layout experiments, which is the primary focus of this paper.Starting from a range of existing available power saving options, this work explores the tradeoff and analyzes the results: the design priority tradeoff, the process technology impact, and implementing low-power configurable processor using commercial scaled-VDD cell libraries compatible with mainstream SOC practices. These real processor designs can achieve power dissipation approaching 20μW/MHz at 0.8V and close to 10μW/MHz at 0.6V, using production 0.13um libraries. Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs.

Increasing design cost and risk is causing more and more designers to build configurable platforms that will amortize design and manufacturing costs across many generations. Several reconfiguration schemes exist and none of them seems to be a clear winner. Most notably there are three forms of technology: structured ASIC, configurable software programmable, reconfigurable FPGA-like platform. New solutions are emerging and may induce drastic changes in the current industry organization. The panel will examine factors in the success of the various options, and look to what the future might bring.

This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI by using configurable processors to implement on-chip functions while increasing the SOC's flexibility through software programmability. The essential enabler for this design methodology is automatic processor generation-the rapid and easy creation of new microprocessor architectures, complete with efficient hardware designs and comprehensive software tools. The high speed of the generation process and the great flexibility of the generated architectures underpin a fundamental shift of the role of processors in system architecture.

Summary form only given. As VLSI technology advances, it forces changes in the business organization of the industry. Traditional vertically integrated semiconductor manufacturers are concentrating less on manufacturing as foundries such as TSMC, UMC, and Chartered grow. These foundries supply capacity not only to fables houses but also to even large semiconductor manufacturers. As a result, these semiconductor houses are spending more time creating novel platforms for important applications. This puts them in competition with the systems houses that traditionally were their customers.

New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Automated extension of processor function units and the associated software environment - compilers, debuggers, simulators and real-time operating systems - satisfies these needs. At the same time, designing at the level of software and instruction set architecture significantly shortens the design cycle and reduces verification effort and risk. This paper describes the key dimensions of extensibility within the processor architecture, the instruction set extension description language and the means of automatically extending the software environment from that description. It also describes two groups of benchmarks, EEMBC's Consumer and Telecommunications suites, that show 20 to 40 times acceleration of a broad set of algorithms through application-specific instruction set extension, relative to high performance RISC processors.

Advances in device technology have led to an era where entire systems can be implemented on a single component, commonly referred to as system-on-chip. With shrinking product life cycles placing severe time to market demands on manufacturers, coupled with their need to quickly change a product's feature set to address evolving customer requirements, programmability will emerge as a corner-stone for all chips implemented in the future. The Internet, communications, consumer electronics, and computing markets are first to take advantage of system-on-chip technology. What are the benefits of programmability to these and other markets and are there potential pitfalls? What architectures and programmability (or reconfigurability) are going to be the likely winners and at what cost? Are these architectures likely to converge or diverge? The panelists will debate the merits of their existing approaches and how they are likely to be shaped in the future.

No abstract available.

MIPS is a 32-bit processor architecture that has been implemented as an nMOS VLSI chip. The instruction set architecture is RISC-based. Close coupling with compilers and efficient use of the instruction set by compiled programs were goals of the architecture. The MIPS architecture requires that the software implement some constraints in the design that are normally considered part of the hardware implementation. This paper presents experimental results on the effectiveness of this processor as a program host. Using sets of large and small benchmarks, the instruction and operand usage patterns are examined both for optimized and unoptimized code. Several of the architectural and organizational innovations in MIPS, including software pipeline scheduling, multiple-operation instructions, and word-based addressing, are examined in light of this data.

A new system for logic synthesis and VLSI layout, the Stanford Weinberger Array Minimizer and Implementor (SWAMI), has been developed. This paper describes the system's algorithms and presents preliminary results. The minimization of logic expressions uses local sum-of-products minimization, kernel factorization and common subexpression recognition and generates improved expressions of arbitrary depth. Logic expressions are realized in nMOS technology using one dimensional Weinberger array structures or a new extension of Weinberger arrays to two dimensions. The placement phase uses heuristic techniques, including simulated annealing. MIN-CUT linear arrangement and local constructive clustering.