A multi-chip custom digital super-computer called eBrain for simulating Bayesian Confidence Propagation Neural Network (BCPNN) model of the human brain has been proposed. It uses Hybrid Memory Cube (HMC), the 3D stacked DRAM memories for storing synaptic weights that are integrated with a custom designed logic chip that implements the BCPNN model. In 22nm node, eBrain executes BCPNN in real time with 740 TFlops/s while accessing 30 TBs synaptic weights with a bandwidth of 112 TBs/s while consuming less than 6 kWs power for the typical case. This efficiency is three orders better than general purpose supercomputers in the same technology node.

In this paper, we present an SC filter for RF down-conversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.12 mum CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included

A method to mitigate timing problems due to global wire delays is proposed. The method follows closely a fully synchronous design flow and utilizes only true digital library elements. The design is partitioned into isochronous blocks at system level, where a few clock cycles latency is inserted between the isochronous blocks. This latency is then utilized to automatically mitigate unknown global wire delays, unknown global clock skews and other timing uncertainties occurring in backend design. The new method is expected to considerably reduce the timing closure effort in large high frequency digital designs in deep submicron technologies.

Full-custom design is considered superior to standard-cell design when a high-performance circuit is requested. The structured routing of critical wires is considered to be the most important contributor to this performance gap. However, this is only true for bitsliced designs, such as ripple-carry adders, but not for designs with inter-bitslice interconnections spanning several bitslices, such as tree adders and reduction-tree multipliers. It is found that standard-cell design techniques scale better with the data width than full-custom bitsliced layouts for designs dominated by inter-bitslice interconnections.

Models of electrical interconnects, including inductance and skin effect, are reviewed. The models are used for estimating the performance of electrical interconnects, particularly related to delays, data rates, and power consumption for off-chip and on-chip interconnects and for clock distribution. It is demonstrated that correctly utilized, electrical interconnects do not severely limit chip or circuit board capacity. Delays, data rates, and power consumption of electrical interconnects within a circuit board are acceptable and superior to optical alternatives.

In this paper, interconnection length estimation is discussed and a general, simple, fast and efficient estimation technique is proposed. In contrast to traditional average length estimation techniques, such as the one based on Rent's rule, the new technique utilizes the topological information of the actual netlist and estimates the length of each interconnection separately. The result of the estimation can be directly used to assign a reasonable R and C to each interconnect, including long and wide buses. Consequently, the new technique enhances the accuracy of power and delay estimations at higher design levels of abstraction.

The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and accumula?tions, is analyzed. An implementation is proposed, composed of switched-capacitor mixed analog/digital multiply accumulate units in the analog front-end, followed by an A/D converter. This imple?mentation is shown to be superior in respect of power consumption compared to an equivalent implementation with a high-speed A/D converter in the front-end, to execute signal processing tasks that include decimation. The power savings are only due to relaxed requirement on A/D conversion rate, as a direct consequence of the decimation. In a case study of a narrowband FIR filter, realized with four multiply accumulate units, and with a decimation factor of 100; power saving is 54 times. Implementation details are given, the power consumption, and the thermal noise are analyzed.

Communications between processing elements (PEs)in very large scale parallel systems become more challenging as the function and speed of the PEs improve continuously. Clocked I/O ports may malfunction if data read failure occurs due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughput, less power consumption in clock distribution, no constraints on clock skew and system scale, easy in design, less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, a robust vector transfer between PEs with arbitrary clock phases is achieved and the headache problem of the global synchronization is avoided.

In very high-speed CMOS cell design, the result of schematic simulation is inaccurate because of missing parasitic components, such as diodes and parasitic capacitances. Designer cannot pass enough information to the simulator by conventional transistor symbols, therefore, simulation error occurs. In this paper, we address a layout-based schematic (LBS) method for high-speed CMOS cell design. In this method, we introduce several types of MOS transistors and estimate parasitic wire capacitances by using layout knowledge. The simulation results show that the difference between LBS and real layout is much smaller, less than 3% in rise time, compared to in the worst case of up to 65% in the original schematic. This method can be applied to both digital and analog circuits and it is helpful for layout automation. Time and cost will be reduced in high-speed circuit design.

Communications between processing elements (PEs) in high speed parallel systems become a bottleneck as the function and speed of the PEs improve continuously. Clocked I/O ports in PEs may malfunction if data read failure occurs due to clock skew. To reduce the clock skew, global clock distribution is utilized, however it seems to be more difficult to use this for high speed parallel systems in the future. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. This method has these features: high data throughput; low power consumption; no constraints on clock skew and system scale; flexibility in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. Using a jitter injected test signal, robust vector transfer between PEs with arbitrary clock phases is achieved without global synchronization.

In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a V/sub dd/ close to V/sub T/ and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low V/sub dd/. To avoid reducing V/sub dd/ below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to V/sub T/ based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.

One of many important factors affecting power consumption is the choice of circuit technique for logic, latches and flip-flops. We analyze the power consumption at circuit level and use the results to guide the choice of circuit technique. Several types of latches and flip-flops are compared regarding power consumption and speed. Comparing logic clearly indicates that simple static logic in general have the lowest power consumption. Another very important factor affecting power consumption is the supply voltage. We discuss the effect of low supply voltage on the choice of circuit technique.

The near-sensor image processing concept, which has earlier been theoretically described, is here verified with an implementation. The NSIP describes a method to implement a two-dimensional (2-D) image sensor array with processing capacity in every pixel. Traditionally, there is a contradiction between high spatial resolution and complex processor elements, In the NSIP concept we have a nondestructive photodiode readout and we can thereby process binary images without loosing gray-scale information. The global image processing is handled by an asynchronous Global Logical Unit. These two features makes it possible to have efficient image processing in a small processor element. Electrical problems such as power consumption and fixed pattern noise are solved. All design is aimed at a 128/spl times/128 pixels NSIP in a 0.8 /spl mu/m double-metal single-poly CMOS process. We have fabricated and measured a 32/spl times/32 pixels NSIP. We also give examples of image processing tasks such as gradient and maximum detection, histogram equalization, and thresholding with hysteresis. In the NSIP concept automatic light adaptivity within a 160 dB range is possible.

High speed time-division multiplexers and demultiplexers are important components of modern optical communication systems. They are needed to parallelize the data to allow most of the system to operate at much lower speeds. This paper describes a 16:1 multiplexer and a 1:16 demultiplexer implemented on one IC in a 1.2 /spl mu/m BiCMOS process. The IC combines fast ECL circuits with CMOS circuits, demonstrating that by utilizing the combination of bipolar and MOS transistors, a VLSI circuit with very high speed interface is feasible.>

Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed.>

The nonrestoring pass transistor EXOR gate is investigated by switch-level simulation. It is shown that the logical function of the EXOR gate depends on the driving conductance on the inputs to the gate. It is also shown why switch-level simulators are unsuccessful in simulating the pass transistor EXOR gate, and how a switch-level simulator can be designed to produce a correct simulation result.>

A new algorithm for switch-level simulation is suggested which allows the simulator to be fully dynamic, i.e., several signals may propagate in the network simultaneously. It is shown how this algorithm can be combined with a timing model. Finally, it is demonstrated how a simulator based on this algorithm can handle problems such as charge sharing and clock skewing in general CMOS circuits.