Monitoring patients with heart disease can be done by analyzing the electrocardiogram (ECG). However, the large amount of data poses a burden for a system that is implemented as an Internet of Things system with limited memory and computation capabilities. Traditionally, lossless compression methods have been favored to reduce the memory requirements due to the critical nature of the application. However, if the reconstruction of a lossy signal does not significantly affect diagnosis capability, then those methods may become attractive due to their larger compression ratios (CRs). In this article, we propose a hybrid lossy/lossless compression system with good signal fidelity and CR characteristics. The performance is evaluated after decompression using deep neural networks (DNNs) that have been shown to have good classification capabilities. For the Clinical Outcomes in Digital Electrocardiology (CODE) data set, the proposed hybrid compressor can achieve an average CR of 5.18 with a mean-squared error (MSE) of 0.20, and DNN-based diagnosis of the decompressed waveforms has, on average, only 0.8 additional erroneous diagnoses out of a total of 402 cases compared to using the original ECG data. For the PTB-XL data set, the hybrid compressor can achieve a high average CR of 4.91 with an MSE of 0.01. In addition, the decompressed ECGs have only a 2.46% lower macro averaged area under the receiver operating characteristic curve (AUC) score than when using the original ECGs.

Customized hardware based convolutional neural network ( CNN or ConvNet ) accelerators have attracted significant attention for applications in a low-cost, edge computing system. However, there is a lack of research that seeks to optimize at both the algorithm and hardware levels simultaneously in resource-constrained FPGA systems. In this paper, we first analyze ConvNet models to find one that is most suitable for a low-cost FPGA implementation. Based on the analysis, we select MobileNetV2 as the backbone of our research due to its hardware-friendly structure. We use a quantized implementation with 4-bit precision and optimize further with a smaller input resolution of 192 × 192 to obtain a 68.8% detection accuracy on ImageNet, which represents only a 3.2% accuracy loss compared to a floating-point model that uses the full input size. We then develop a hardware implementation that uses a low-cost FPGA. To accelerate the depth-wise separable ConvNet and utilize DRAM resources efficiently with parallel processing, we propose a novel scoreboard architecture to dynamically schedule DRAM data requests in order to maintain a high hardware utilization. The number of DSP blocks used is about six times smaller than in prior work. In addition, internal block RAM utilization is approximately nine times more efficient than in prior work. Our proposed design achieves 3.07 frames per second (FPS) on the low-cost and resource constrained FPGA system.

In this paper, a general feedback structure is proposed to improve the performance of existing digital notch filters. With the feedback structure, the notch filter can have a narrower stopband. This structure can be applied to any type of existing notch filter. We first derive the improved design of existing one-dimensional (1-D) filters. Then, by suitably extending the 1-D concept, the design of two-dimensional (2-D) notch filters is also derived. To demonstrate the effectiveness of the proposed design, an experiment on the interference removal of an image is presented. Moreover, a new forward and reverse algorithm for 2-D image filtering is proposed to reduce the transient error and enhance the signal-to-noise ratio drastically.

Nonorthogonal multiple access technology has been proposed for use in 5G communications systems. In particular, the sparse code multiple access (SCMA) scheme is believed to be one of the most promising techniques among the various nonorthogonal approaches that have been investigated. In this letter, we focus on reducing the complexity of SCMA decoding and we propose a Monte Carlo Markov Chain (MCMC) based SCMA decoder. Benefiting from the linearly increasing complexity of the MCMC method, the proposed SCMA decoder has only 10% of the computational load compared to previous state-of-the-art methods when the codebook size is 64. Consequently, the MCMC SCMA decoder has great potential for use in practical system implementations.

Intrabody communication has been of great research interest in recent years. This paper proposes a novel, compact but accurate body transmission channel model based on RC distribution networks and transmission line theory. The comparison between simulation and measurement results indicates that the proposed approach accurately models the body channel characteristics. In addition, the impedance-matching networks at the transmitter output and the receiver input further maximize the power transferred to the receiver, relax the receiver complexity, and increase the transmission performance. Based on the simulation results, the power gain can be increased by up to 16 dB after matching. A binary phase-shift keying modulation scheme is also used to evaluate the bit-error-rate improvement.

The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions.

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed-area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18-μm technology are also provided.

In this paper we propose a high performance bidirectional path preserving trellis search (PPTS) detector for multiple-input-multiple-output (MIMO) systems. The error analysis between single direction and bidirectional PPTS detector is given. We prove that the bidirectional PPTS detector can minimize the detection error effectively. Moreover, the proposed detector saves 10% hardware cost with a 0.1 dB Frame Error Rate (FER) gain compared with traditional PPTS detectors.

Compared with traditional Fast Fourier Transform (FFT) algorithms, FFT pruning is more computationally efficient in those cases where some of the input values are zero and/or some of the output components are not needed. In this letter, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.

This paper presents a high-throughput memory- efficient decoder architecture for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high-rate wireless personal area network applications. Two novel techniques which can apply to our selected QC-LDPC codes are proposed, including four-parallel block layered decoding architecture and simplification of the switch networks. The proposed architecture based on a block parallel decoding scheme replaces a crossbar- based interconnect network with a fixed wire network for a switch network. In addition, two-stage pipelining is used to improve the clock speed. A 672-bit, rate-1/2 LDPC decoder is implemented using 90 nm CMOS technology. The design achieves an information throughput of 1.45 Gbps at a clock speed of 285 MHz with a maximum of 16 iterations.

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.

In this paper, we propose a novel frequency domain adaptive tap partial update algorithm for network echo cancellation. Controlled by a simple sparseness measurement of the filter coefficients, the new algorithm adapts not only the filter coefficients, but also the number of taps to be updated iteration by iteration. Using the convergence behavior of the sparseness measurement, the proposed algorithm regards the convergence of the filter coefficients as a two-stage process incorporating the MMax and SPMMax partial update criteria together with the improved proportionate multi-delay filtering (IPMDF) and multi-delay filtering (MDF) adaptive algorithms. Simulation results show that, compared with fully updated IPMDF, our proposed algorithm achieves the same convergence performance with significantly reduced computational complexity.

The Network-on-Chip (NoC) concept has been proposed to replace conventional bus-based system architectures to create scalable and flexible future SoC designs. A 2D-mesh topology is one of the most frequently mentioned topologies for an NoC design due to its natural layout mapping onto an SoC. However, the 2D-mesh topology NoC has a hot-spot problem at the center of the network and presents difficulties in multicasting. In this paper, we propose a novel multicastable CDMA switch and an efficient mesh-star hybrid topology. This approach leads to reduced traffic at the center of the network and better performance with multicasting. Our switch has been synthesized using a 0.13µm CMOS technology library.

In this paper, we present adaptive quantization schemes in the normalized min-sum decoding algorithm considering scaling effects to improve the performance of irregular low-density parity-check (LDPC) decoder for WirelessMAN (IEEE 802.16e) applications. We discuss the finite precision effects on the performance of irregular LDPC codes and develop optimal finite word lengths of variables over an SNR. For floating point simulation, it is known that in the normalized min-sum or offset min-sum algorithms the performance of a min-sum based decoder is not sensitive to scaling in the log-likelihood ratio (LLR) values. However, when considering the finite precision for hardware implementation, the scaling affects the dynamic range of the LLR values. The proposed adaptive quantization approach provides the optimal performance in selecting suitable input LLR values to the decoder as far as the tradeoffs between error performance and hardware complexity are concerned.

We present a MIMO joint transceiver design that can run at 350 MHz on a Xilinx Virtex-4 xc4vlx200ffl513-12 FPGA. The implementation is an 8 times 8 MIMO transceiver with a 16-QAM symbol constellation. This system can provide data throughput of 11.2 Gbps. The design is based on a modified geometric mean decomposition (GMD) for a flat fading MIMO channel using VBLAST MIMO detection. The design flow uses Matlab Simulink as the model builder followed by the Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.

We present a digital hardware model for ultra wideband channels. The system runs at 80 MHz on a Xilinx Virtex-4 xc4vsx35 FPGA. High-speed arithmetic operations including division, square root, powering and normal random number generator are analyzed and developed for use as basic components in the channel emulator. The design flow is based on Matlab Simulink as the model builder, followed by Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs

Pulsed OFDM (P-OFDM) is a proposed enhancement to Multi-Band Orthogonal Frequency Division Multiplexing which reduces the power and complexity of Ultra Wideband transceivers without sacrificing performance. In this paper, the effects of finite precision arithmetic in the mixed-radix Fast Fourier Transforms of P-OFDM architectures are analyzed using a noise model. The results of this analysis lead to the selection of optimal values for the wordlengths of the data and coefficients. Synthesis results based on these optimal wordlengths are presented for a Xilinx Virtextrade-4 FPGA implementation.

Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mixed-signal design combined with a behavioral description language and mixed-mode simulations. The use of Verilog-AMS is applied not only to circuit modeling but also for representing noise on the input signal. This approach provides system-level jitter tolerance estimation, circuit critical path search and overall design verification. Coding examples and simulation results are included.

Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection networks plays a critical role in shared memory MPSoC designs. In this paper, we propose a directory-cache embedded switch architecture with distributed shared cache and distributed shared memory. It is able to reduce the number of home node cache accesses, which results in a reduction in the inter-cache transfer time and the total execution time. Simulation results verify that the proposed methodology can improve performance substantially over a design in which directory caches are not embedded in the switches.

Providing quality-of-service (QoS) in networks-on-chip (NoCs) is an important consideration for the complex multiprocessor chips of the future. In this paper, we discuss the difficulties encountered in addressing these requirements. Then, we propose a promising solution to this problem that is based on applying the well-known MPLS technology of large-scale computer networks to the on-chip environment. A network simulator is used to evaluate the concept for a typical communications scenario that must support several classes of traffic having a range of QoS requirements.

The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP cores. In this paper, we present a novel NIU architecture that utilizes a Gray code based packet reordering methodology to achieve low latency packet processing. The proposed architecture has been implemented with VHDL and synthesized using a 0.25 /spl mu/m ASIC technology. Simulation results verify the functionality of the architecture and show that it can save a substantial amount of packet processing time compared to the conventional reordering scheme.

This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links between adjacent routers and links between a router and an attached processing element (PE). Analytical models for global router-to-router links and semi-global router-to-PE links are studied. Power and performance optimizations are obtained for each of these two classes of interconnections.

This paper presents timing and area results for an FPGA implementation of a CDMA-based switch for networks-on-chip. The design was mapped onto the Xilinx Virtex4 XC4VLX200 device using Synplify Pro for a range of pay-load sizes. The synthesis results give the area and maximum frequency obtained. Simulation verifies the desired functionality and provides throughput and latency values as functions of payload size.

Due to the spectrum gap between subcarriers in an UWB-OFDM system, an N-tone sigma-delta modulator can be used to introduce appropriately placed nulls into the noise spectrum of such systems. The resulting performance is evaluated in terms of in-band quantization noise and excess resolution gained. Moreover, we relate the performance of our system to that of a traditional oversampled sigma-delta modulator operating in a lowpass system. A higher-order N-tone sigma-delta modulator having better noise shaping ability is also introduced for use in UWB-OFDM systems.

Presents results on using advanced domino circuit design techniques to implement a CORDIC processor. Skew-tolerant domino, enhanced precharged contention, nonblocking domino and pulsed reset domino circuit techniques are explained and applied to the implementation of this functional unit. For comparison purposes, a baseline design using standard two-phase domino with intermediate latches is also developed. Simulation results show that significant throughput improvement is possible using the advanced circuit techniques, with the pulsed reset style having the highest speed. On the other hand, these approaches result in increased power dissipation.

A novel connection between digit-serial computing and skew-tolerant domino circuit design is developed and applied to the design of a 512-bit modular multiplier. In our design, a digit size of four bits is efficiently mapped onto a four-phase overlapping clocking scheme, so that four bits are processed during each full clock cycle. Our architecture is based on a modified interleaved multiplication algorithm and uses precomputed complements of the modulus and a carry save adder scheme. We also present a technique for modeling the time borrowing behavior in skew-tolerant domino using a VHDL behavioral description. This allows very large skew-tolerant domino circuits to be simulated efficiently in such a way that the essential time borrowing behavior is correctly represented. This simulation methodology is used to verify the correctness of our design and to determine its throughput.

In this paper, we present a new architecture for an electronic implementation of an ATM switch using a technique from spread spectrum communications known as Code Division Multiple Access (CDMA). In a CDMA-based ATM switch, each output port is assigned a unique code word from an orthogonal set of code words. Each input data stream is encoded using the code word corresponding to its intended destination output port. Coded data from different input ports are then added together and broadcast to all of the output ports. Each output port is able to select its appropriate data stream using coding theory. In this way, complex internal routing within the switching fabric is avoided. In our basic method, the input data are expanded by a factor equal to the number of bits in a code word. A second, more sophisticated method called exponential extension is also introduced to reduce the data expansion rate so that more efficient hardware implementations can be obtained.

We present results on time borrowing in skew-tolerant domino logic circuits for a 32-bit adder, a 64-bit adder and a 32-bit pipelined multiplier. The adders are built using enhanced multiple output domino logic and the multiplier uses modified Booth encoding and a Wallace tree. We illustrate how the resulting soft clock edges allow advantageous time borrowing to occur in these functional units. In this way, limitations due to delay imbalances between stages are removed, allowing the circuits to operate at a higher speed.

Elliptic curve (EC) cryptosystems have become more attractive due to their small key sizes and varieties of choices of the curves available. However, it is not efficient to implement them with a general-purpose microprocessor because of word size mismatch, less parallel computation, no hardware supported wire permutation and algorithm/architecture mismatch. The solution to this problem is to build a coprocessor. This coprocessor can be optimized for the algorithm of a particular application to enhance performance. Thus, the total hardware utilization can be kept at a very high rate and the computation is speeded up. A compact fast elliptic curve crypto coprocessor with variable key size is introduced, which utilizes the internal SRAM/registers in an FPGA. The generic hardware architecture for the coprocessor is implemented with a parameterized (in term of key size) VHDL description and is synthesized/mapped to a Xilinx FPGA. The algorithms adopted and the architecture developed are suitable for massively parallel computation. The experimental results show that the design can achieve a high utilization of CLBs for the Xilinx 4000 series.

This paper gives the digit-serial DSP libraries used to implement the digit-serial DSP architecture for field programmable gate arrays (FPGAs) and compares schematic-based FPGA design with design based on logic synthesis for digit-serial DSP libraries. It describes the design of digit-serial addition/subtraction, multiplication and delay elements and indicates also how digit-serial FIR filter can be implemented. The FPGA device utilization and critical path delay of digit-serial DSP libraries are calculated and described.

No abstract available.

A new circuit based on combining XOR gates and double pass-transistor logic has been developed for implementing a full adder. The main design objectives for these new circuits are low power consumption and full-voltage swing at a low supply voltage. The proposed full adder circuit is compared with previously known circuits and is shown to provide superior performance. The new and previous full adder circuits have been fully simulated using HSPICE with 0.4 /spl mu/m CMOS technology at a 2.0 V supply voltage. An extensive analysis of a 8-bit carry-select adder establishes the superiority of the proposed circuit in that application.

A circuit design technique for very low power parallel multipliers is presented. The design uses dynamic CMOS circuits together with a self-timed evaluate signal in such a way that each carry-save or carry-propagate adder within the array evaluates only after all of its inputs have stablized. This technique avoids the spurious switching of internal nodes so that the average power dissipation is minimized. Circuit simulation results are presented which illustrate the power dissipation characteristics of the multiplier.

The utility of modern symbolic computation packages in a course of convolution and discrete Fourier transform (DFT) algorithms is presented. It is shown how Mathematica has been used to help illustrate the number-theoretic, polynomial, and finite-field computations involved. The result is that students are relieved of much of the algebraic drudgery and can concentrate on learning the fundamental aspects of the subject. It has been found that large problems can be successfully solved by students in a way that they find to be both interesting and satisfying. In addition, symbolic verification techniques can be used to prove the correctness of the results that are obtained.>

A new class of fault simulation algorithms, that have recently been developed for gate-level fault simulation and shown to have several advantages over concurrent fault simulation, are adapted for switch-level fault simulation.High speed compiled switch-level simulation is used for circuit evaluation that approaches the speed of gate-level simulation.The fault simulation algorithms are single fault propagation, differential fault simulation, active fault simulation and parallel active fault simulation.Using these algorithms, minimum memory requirements and high simulation efficiency are achieved, both of which are essential to performing practical fault simulation at the switch-level due to the large number of switch-level faults.

A mixed functional/IDDQ testing methodology is presented for detecting transistor faults in CMOS VLSI circuits. A fault preprocessor and a fast switch-level fault simulator have been developed for implementing this testing methodology. The fault preprocessor performs fault generation and collapsing of CMOS transistor faults and identifies those transistor faults that are undetectable by functional testing. Faults that are detectable by functional testing are simulated by the switch-level fault simulator using logic monitoring of the circuit outputs. Faults that are deterministically undetectable by functional testing are considered for detection by monitoring the IDDQ current. These faults are detected if they create conducting transistor paths between VDD and GND, thus elevating IDDQ. By using accurate electrical evaluation techniques of the switch-level circuit state the number of faults that are determined to be detectable by functional testing is increased and the corresponding number of faults requiring IDDQ testing is decreased. This decreases the number of test vectors where IDDQ testing is required and therefore minimizes the total test time.

A novel switch-level fault simulation method is presented for MOS circuits that combines compiled switch-level simulation techniques with functional fault modeling. The simulator models both node stuck-at-zero, stuck-at-one faults and transistor stuck-on, stuck-open faults. During compilation the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level and is shown to perform well, although it incurs a higher overhead due to the dynamic memory properties of MOS circuits.>

In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computationally efficient and produces test generation circuitry with low hardware overhead is proposed. The effectiveness of this approach is demonstrated by detailed comparisons of its results with those that would be obtained by existing techniques.>

The FPC (floating-point process controller) chip design and the AMD Am29325 32-b floating-point processor mathematics chip form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-b instruction word that provides concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams. The novel architectural features of the cell are described, and a matrix multiplication example is used to demonstrate their usefulness.>

SAC (systolic array controller) is a chip designed for use with an NCR 16-bit fixed-point multiplier/accumulator (MAC) chip to form a two-chip cell in systolic arrays for signal processing applications. The SAC/MAC cell can be used as an inexpensive, flexible building block for either one-dimensional or two-dimensional systolic arrays in either application-specific or general-purpose machines. The SAC provides an interface to other cells via four parallel ports. It routes data to and from the companion high-speed MAC via one 16-bit bidirectional port, controls the MAC, and provides 64 words of scratchpad memory for programs and data.>

In this paper, we present algorithms and experimental results for an automated layout synthesis procedure that is used in a high-level silicon compiler. The techniques consist of a unique approach to generalized cell synthesis, together with a novel solution of the placement and routing problem. Our algorithms take advantage of a larger space of possible solutions than is available in conventional, fixed-cell approaches to achieve compact and efficient layouts.

In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface logic. A novel technique for layout generation yields cells whose densities approach hand-crafted designs. Two-layer metal NMOS and CMOS technologies are supported, with flexible design rules. In addition to layout synthesis, logic, schematic and graph diagrams are generated directly from a powerful internal data base. The compiler, which runs under the UNIX^^ operating system, includes a menu-driven multi-windowing user environment.

An automated system has been developed for use in the characterization and modeling of MOS transistors. The system, consisting of automatic testing, a dynamic data base, and device parameter extraction, has been applied to process characterization and device modeling. The data base handles storage and retrieval of the data. Parameter extraction is based on optimization with constraints.