Convolutional neural networks (CNNs) have demonstrated outstanding accuracy among a range of machine learning tasks. However, the huge computational overhead limits their deployability in real-time applications. For this reason, parallel computing has been extensively employed to accelerate CNNs in parallel computing devices, such as GPUs and field programmable gate arrays (FPGAs), by unrolling multiple loop operations of convolutional layers. Nevertheless, existing CNN accelerators can hardly exploit different parallelisms offered by the CNN algorithms efficiently, since their degrees of parallelism are fixed at different dimensions and layers. In this article, we propose the DCP-CNN, an FPGA-based CNN accelerator which implements the CNN with Dynamic Computing Parallelism degrees. DCP-CNN employs a parallel computing architecture which dynamically allocates the computing resources between different data dimensions of each layer based on layer size, to ensure that all computing units are working to full capacity and thus achieve optimal compute efficiency (CE). Furthermore, in order to boost the performance of throughput, we propose a design space exploration (DSE) framework based on the simulated annealing method, which automatically generates the parallelism degrees between different dimensions of the network layers, according to the resource constraints and CNN structure. On Intel Stratix 10 GX650 FPGA, the proposed DCP-CNN achieves the throughput of more than 800 Gop/s and the CE of 72%–98%, which outperforms the existing state-of-the-art FPGA-based CNN accelerators.

This paper describes a new silicon physical unclonable function (PUF) using thyristor components that can be fabricated on a standard CMOS process. Our proposed design is built using thyristor-based sensors, time difference amplifier (TDA), time difference comparator, voting mechanism, and diffusion algorithm circuit. Multiple identical thyristor-based sensors are fabricated on the same chip. Due to the manufacturing process variations, each sensor produces two slightly different delay values that can be compared in order to create a digital identification for the chip. Diffusion algorithm circuit further ensures that the proposed PUF is able to effectively identify a population of integrated circuits. We also improve the stability of PUF design with respect to temporary environmental variations, such as temperature and supply voltage with the introduction of TDA and voting mechanism. The thyristor-based PUF is fabricated in a 0.18-$\mu \text{m}$ CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of a uniform distribution and a high stability of 96.8% with respect to temperature variation from -40 °C to 100 °C, and supply voltage variation from 1.7 to 1.9 V.

With mobile and wireless devices becoming pervasive, low-cost hardwares of security functions are being desired. A compact hardware implementation of the SM3 hash algorithm is presented in this paper. A SRAM is used to do message expansion function instead of shift registers which are used in common hardware implementations, and the values of A~H and V0~V7 registers are updated in the serial shift way when they are initialized and updated. The computation units are saved as much as possible. Compared with traditional designs, the store resources for message expansion function can be shared with other modules to reduce the cost of a system. The Synopsys' DC synthesis results show that the area of the compact SM3 is approximate 8277 GEs while its throughput can be as high as 276 Mbps. If the SRAM is shared with other modules, only 6904 GEs are required to implement the SM3 hardware module in the system. The compact architecture can be accommodated to resource-constrained systems for its advantages of low-cost and low-power.

The fast Fourier transform (FFT) is a fundamental kernel of many computation-intensive scientific applications. This paper deals with an implementation of the FFT on the accelerator system, a heterogeneous multicore architecture to accelerate computation-intensive parallel computing in scientific and engineering applications. The Engineering and Scientific Computation Accelerator (ESCA) consists of a control unit and a single instruction multiple data (SIMD) processing element (PE) array, in which PEs communicate with each other via a hierarchical two-level network-on-chip (NoC) with high bandwidth and low latency. We exploit the architecture features of ESCA to implement a parallel FFT algorithm efficiently. Experimental results show that both the proposed parallel FFT algorithm and the ESCA architecture are scalable. The 16-bit fixed-point parallel FFT performance of ESCA is compared with a published work to prove the superiority of the mapping algorithm and the hardware architecture. The floating-point parallel FFT performances of ESCA are evaluated and compared with those of the IBM Cell processor and GPU to demonstrate the computing power of the ESCA system for high performance applications.

As a free application programming interface (API) for hardware-accelerated two-dimensional vector and raster graphics, OpenVG is becoming the standard for hardware development. This paper firstly proposes several optimization methods for OpenVG implementation, such as loop unrolling, operation transformation, function in lining, vectorization and address assignment, based on the hardware architecture and programming model of the Synchronous Data Triggered Architecture (SDTA). We then optimally realize the OpenVG path and paint algorithms on the SDTA with the direction of these methods and consideration of the algorithmspsila characteristics. The analysis results show that the optimized OpenVG algorithms achieved 3-9 times speedups compared with original ones.

Multi-core processor has become hot research area recently. Cache results in high cost to maintain consistency between different data copies in multi-core processor especially in many-core processor. A hybrid memory architecture is proposed for the specific multi-core processor which uses cache for instruction while local storage for data. This paper focuses on the design and optimization of the proposed memory architecture. L1 instruction cache, local data storage, DMA engine, L2 cache and MMU is designed and optimized. L2 cache replacement strategy is studied to reduce the total miss cost.

In this paper, the dynamically-allocated virtual channels (VCs) architecture with congestion awareness is introduced. All the buffers are shared among VCs whose structure varies with traffic condition. In low rate, this structure extends VC depth for continual transfers to reduce packet latencies. In high rate, it dispenses many VCs and avoids congestion situations to improve the throughput. We modify the VC controller and VC allocation modules, while designing simple congestion avoidance logic. The experiment shows that the proposed routers outperform conventional ones under different traffic patterns. They provide 8.3% throughput increase and 19.6% latency decrease while saving 27.4% of area and 28.6% of power.

To address the increasing susceptibility of microprocessors to transient faults, many techniques have been proposed to exploit the core redundancy of chip multiprocessors (CMPs). But the inter-core communications become critical in these core redundancy based techniques. To reduce the inter-core communication bandwidth demand, two new approaches, dual core redundancy (DCR) and triple core redundancy (TCR), are proposed for fault tolerance in this paper. In DCR, only store instructions are compared before commit, so that the bandwidth demand can be largely reduced. And the fault recovery is achieved by context saving and recovery. While TCR applies triple modular redundancy (TMR) in the core level to efficiently exploit the core resources of CMPs for transient fault masking. In TCR, only the results of store instructions are compared to detect transient fault and reduce the inter-core communication bandwidth demand. Once detecting a single event upset (SEU), TCR can be reconfigured to execute with the two uncorrupted cores for fault detection.The experimental results demonstrate that compared to traditional transient fault recovery scheme CRTR, both DCR and TCR efficiently reduce inter-core bandwidth demand. DCR achieves transient fault recovery with reasonable performance overhead caused by context saving. TCR occupies more core resources and has the lowest performance overhead during normal execution.

The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This paper proposes a new architecture for the MAF unit that supports multiple IEEE precisions multiply-add operation (AtimesB+C) with Single Instruction Multiple Data (SIMD) feature. The proposed MAF unit can perform either one double-precision or two parallel single-precision operations using about 18% more hardware than a conventional double-precision MAF unit and with 9% increase in delay. To accommodate the simultaneous computation of two single-precision MAF operations, several basic modules of double-precision MAF unit are redesigned. They are either segmented by precision mode dependent multiplexers or attached by the duplicated hardware. The proposed MAF unit can be fully pipelined and the experimental results show that it is suitable for processors with floatingpoint unit (FPU).

Current information security prevention system has some disadvantages, such as the singleness of the data source, the imperfectness of the architecture and the absence of alert information post-processing. To address these, we present a framework for security event management based on mobile agent technology. In the framework, various agents are designed for different functions and roles, and these agents can communicate and collaborate securely. By virtue of the autonomy, mobility, inferential capability and social ability of the mobile agent, the numerous security events which may appear at many locations in the network can be efficiently detected, verified by the sensor agent and the verification agent. Furthermore, the correlation agent can correlate the purified security events globally based on the temporal relation, the causal relation, the spatial relation and statistics relations among them. We select Aglet as the platform and develop a security event management system (SEMS). Finally, through some multi-step attack scenarios, the effectiveness and the advantages of the mobile agent technology used for security event management have been verified.

Realizations of demanding embedded applications particularly in the field of signal processing often require high processing performance and low energy consumption which are far beyond what can be delivered by DSPs nowadays. A novel data-parallel coprocessor basing on the transport triggered architecture (TTA) is presented in this paper. The coprocessor consists of two powerful arithmetic clusters, the stream memory as well as the optimized data transport network, and is good at exploiting the data parallelism in the computation intensive multimedia applications. Also, the solution of the clock-gating in a gradual way is advanced for the low power dissipation. Then, a SoC chip involving the coprocessor is implemented using 0.18 mum CMOS process. Experimental results show that this coprocessor has good performance improvement for multimedia applications

In this paper a RSA crypto coprocessor that is fabricated using a 0.18mum CMOS technology is presented. This processor combines a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation can be decomposed into a series of primitive operation (PO) matrixes. All the POs are scheduled on the pipeline by employing column-sharing strategy, and inside the PO all the partial results are compressed first by Wallace tree to assure only one carry propagation in the critical path. With these optimizations, a decryption rate of 6.35 Mbps can be achieved for 1024-bit RSA

It is well known that H.264 has great advantage of coding efficiency compared with the successful prior coding standards and it can save about 50% bit-rate under the same reconstructed picture quality. But the complexity of H.264 encoder is also very high. In order to improve the speed of the H.264 encoder, this paper researches the intra modes for inter-frame coding. The algorithm of mode decision for inter-frame coding is introduced and the complexity of the H.264 encoder is analyzed from the side of transform and quantization. In order to speed up the H.264 encoder without causing a great decrease in encoding efficiency, a fast intra mode decision method for inter-frame coding is also introduced. The experimental results show that the inter-frame coding with fast intra mode decision can reduce the computational complexity of the H.264 encoder remarkably while incurring little, if any, loss in quality.

With more and more security risks arising in information system, research on the trusted computer architecture becomes a hot topic. Trusted Computing Group (TCG) has made deep research and given specifications of trusted computing platform. However, trusted computer is so different that many software of traditional systems can not run on it without any modification. What's more, users need some time to understand and be familiar with the new system. For these reasons, this paper suggests an alteration scenario for traditional universal computer based on user's USB-KEY, by which users can get almost the same degree of security protection in the general-purpose system. The test result indicates that the universal trust-enhanced computers can assure to be used by authorized users, resist viruses and Trojans and maintain a secure and steady environment for above applications. This scenario costs very lowly, but can easily be put into practice.