This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.

This paper addresses the issue of automatically generating reduced order models of very large multidimensional systems. To tackle this problem we introduce an efficient parallel projection based model order reduction framework for parameterized linear systems. The underlying methodology is based on an automated multidimensional sample selection procedure that maximizes effectiveness in the generation of the projection basis. The parallel nature of the algorithm is efficiently exploited using both shared and distributed memory architectures. This leads to a highly scalable, automatic, and reliable parallel reduction scheme, able to handle very large systems depending on multiple parameters. In addition, the framework is general enough to provide a good approximation regardless of the model's representation or underlying nature, as will be demonstrated on a variety of benchmark examples. The method provides the potential to tackle, in an automatic fashion, extremely challenging models that would be otherwise difficult to address with existing sequential approaches.

This paper proposes a highly efficient methodology for the statistical analysis of RC nets subject to manufacturing variabilities, based on the combination of parameterized RC extraction and structure-preserving parameterized model order reduction methods. The sensitivity-based layout-to-circuit extraction generates first-order Taylor series approximations of resistances and capacitances with respect to multiple geometric parameter variations. This formulation becomes the input of the parameterized model order reduction, which exploits the explicit parameter dependence to produce a linear combination of multiple non-parameterized transfer functions weighted by the parameter variations. Such a formulation enables a fast computation of statistical properties such as the standard deviation of the transfer function given the process spreads of the technology. Both the extraction and the reduction techniques avoid any parameter sampling. Therefore, the proposed method achieves a significant speed up compared to the Monte Carlo approaches.

For integrated circuit (IC) fabrication technologies of 45nm and below, the impact of process variability in circuit performance is extremely relevant. Parametric static timing analysis (PSTA) techniques, whereby delays are modeled as affine functions of process parameters, were thus introduced to enable the computation of accurate timing estimates, accounting for process variability. Most often, only variations that occur between fabricated ICs (inter-die) are modeled, as the number of variables necessary to model such effects is manageable. Variations that occur across the same IC (intra-die) are usually neglected, as modeling them can add significant complexity to the model. This paper evaluates the impact of modeling intra-die variations in the context of PSTA and proposes effective techniques for handling them.

Model Order Reduction is nowadays routinely applied as a basic step in order to enable the efficient simulation of very large RLC linear models, such as extracted parasitics and circuit oriented EM extraction. Often, such reduced models are synthetized as a subcircuit and ported to simulation environments for multiple subsequent runs. Such an approach is quite common as often designers prefer to work with circuit netlists as opposed to abstract mathematical representations and furthermore, many simulators can only handle circuit elements. However, the potential advantages provided by the reduction may be compromised when the dense reduced models are synthetized to netlists due to the presence of non-physical elements (such as negative RLC) or a large number of controlled sources. Such issues may hinder efficiency or even completely preclude analysis as many simulators cannot handle non-physical elements whose handling is altogether questionable. This paper proposes a methodology for the synthesis of reduced order models of general multiport RLC nets amenable to be included in standard simulation environments. Unlike other previously published approaches, the methodology generates very compact models while guaranteeing the positiveness of the RLC values, which allows their direct confinement in any SPICE-like circuit simulator.

This paper presents a methodology for optimizing sample point selection in the context of model order reduction (MOR). The procedure iteratively selects samples from a large candidate set in order to identify a projection subspace that accurately captures system behavior. Samples are selected in an efficient and automatic manner based on their relevance measured through an error estimator. Projection vectors are computed only for the best samples according to the given criteria, thus minimizing the number of expensive solves. The scheme makes no prior assumptions on the system behavior, is general, and valid for single and multiple dimensions, with applicability on linear and parameterized MOR methodologies. The proposed approach is integrated into a multi-point MOR algorithm, with automatic sample and order selection based on a transfer function error estimation. Different implementations and improvements are proposed, and a wide range of results on a variety of industrial examples demonstrate the accuracy and robustness of the methodology.

The clock frequency of a digital IC is limited by its slowest paths, designated by speedpaths. Given the extreme complexity involved in modeling modern IC technologies, often speedpath predictions provided by timing analysis tools are not correct. Therefore, several practical techniques have recently been proposed for design debugging, that combine silicon stepping of improved versions of a circuit with subsequent correlation between measured and predicted data. Addressing these issues, this paper proposes a set of techniques that enable the designer to obtain reduced subsets of paths, guaranteed to contain all the speedpaths of a given circuit or block. Such subsets can be computed either from timing models, prior to fabrication, or incorporating actual delay measurements from fabricated instances.

This paper describes a Model Order Reduction algorithm for multi-dimensional parameterized systems, based on a sampling procedure which incorporates a low order moment matching paradigm into a multi-point based methodology. The procedure seeks to maximize the subspace generated by a given number of samples, selected among an initial candidate set. The selection is based on a global criteria that chooses the sample whose associated vector adds more information to the existing subspace. However, the initial candidate set can be extremely large for high-dimensional systems, and thus the procedure can be costly. To improve efficiency we propose a scheme to incorporate information from low order moments to the basis with small extra cost, in order to extend the approximation to a wider region around the selected point. This will allow reduction of the initial candidate set without decreasing the level of confidence.We further improve the procedure by generating the global subspace based on the composition of local approximations. To achieve this, the initial candidates will be split into subsets that will be considered as independent regions, and in a first phase the procedure applied locally thus enabling improved efficiency and providing a framework for almost perfect parallelization.

An efficient algorithmbased on the Extended Hamiltonian Pencil was proposed in [1] for systems with hybrid representation. Here we further extend the Extended Hamiltonian Pencil method to systems described with scattering representation, i.e. S-parameter systems. The derivation of the Extended Hamiltonian Pencil for S-parameter systems is presented. Some properties that allow passivity enforcement based on eigenvalue displacement are reported. Experimental results demonstrate the effectiveness of the proposed method.

This paper introduces a distributed and shared memory parallel projection based model order reduction framework for parameterized linear systems. The proposed methodology is based on a sampling scheme followed by a projection to build the reduced model. It exploits the parallel nature of the sampling methods to improve the efficiency of the basis generation. The sample selection scheme uses the residue as a proxy for the model error in order to improve automation and maximize the effectiveness of the sampling step. This yields an automatic and reliable methodology, able to handle large systems depending on the frequency and multiple parameters. The framework can be used in shared and distributed memory architectures separately or in conjunction. It is able to deal with different system representations and models of different characteristics, is highly scalable and the parallelization is very effective, as will be demonstrated on a variety of industrial benchmarks, with super linear speed-ups in certain cases. The methodology provides the potential to tackle large and complex models, depending on multiple parameters in an automatic fashion.

Traditional integrated circuit timing sign-off consists of verifying a design for a set of carefully chosen combinations of process and operating parameter extremes, referred to as corners. Such corners are usually chosen based on the knowledge of designers and process engineers, and are expected to cover the worst-case fabrication and operating scenarios. With increasingly more detailed attention to variability, the number of potential conditions to examine can be exponentially large, more than is possible to handle with straightforward exhaustive analysis. This paper presents efficient yet exact techniques for computing worst-delay and worst-slack corners of combinational and sequential digital integrated circuits. Results show that the proposed techniques enable efficient and accurate detection of failing conditions while accounting for timing variability due to process variations.

Modern deep sub-micron ultra-large scale integration designs with hundreds of millions of devices require huge grids for power distribution. Such grids, operating with decreasing power supply voltages, are a design limiting factor and accurate analysis of their behavior is of paramount importance as any voltage drops can seriously impact performance or functionality. As power grid models have millions of unknowns, highly optimized special-purpose simulation tools are required to handle the time and memory complexity of solving for their dynamic behavior. In this paper, we propose a hierarchical matrix representation of the power grid model that is both space and time efficient. With this representation, reduced storage matrix factors are efficiently computed and applied in the analysis at every time-step of the simulation. Results show an almost linear complexity growth, namelyO(n loga(n)), for some small constant a, in both space and time, when using this matrix representation. Comparisons of our academic implementation with production-quality code prove this method to be very efficient when dealing with the simulation of large power grid models.

This paper describes a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parameterized system as a perturbation-like parallel interconnection of the nominal transfer function and the nonparameterized transfer function sensitivities with respect to the parameter variations. Such a formulation reveals an explicit dependence on each parameter which is exploited by reducing each component system independently via a standard nonparameterized structure preserving algorithm. Therefore, the resulting smaller size interconnected system retains the structure of the original system with respect to parameter dependence. This allows for better accuracy control, enabling independent adaptive order determination with respect to each parameter and adding flexibility in simulation environments. It is shown that the method is efficiently scalable and preserves relevant system properties such as passivity. The new technique can handle fairly large parameter variations on systems whose outputs exhibit smooth dependence on the parameters, also allowing design space exploration to some degree. Several examples show that besides the added flexibility and control, when compared with competing algorithms, the proposed technique can, in some cases, produce smaller reduced models with potential accuracy gains.

This paper describes an automatic methodology for optimizing sample point selection for using in the framework of model order reduction (MOR). The procedure, based on the maximization of the dimension of the subspace spanned by the samples, iteratively selects new samples in an efficient and automatic fashion, without computing the new vectors and with no prior assumptions on the system behavior. The scheme is general, and valid for single and multiple dimensions, with applicability on rational nominal MOR approaches, and on multi-dimensional sampling based parametric MOR methodologies. The paper also presents an integrated algorithm for multi-point MOR, with automatic sample and order selection based on the transfer function error estimation. Results on a variety of industrial examples demonstrate the accuracy and robustness of the technique.

Due to higher integration and increasing frequency based effects, full electromagnetic models (EM) are needed for accurate prediction of the real behavior of integrated passives and interconnects. Furthermore, these structures are subject to parametric effects due to small variations of the geometric and physical properties of the inherent materials and manufacturing process. Accuracy requirements lead to huge models, which are expensive to simulate and this cost is increased when parameters and their effects are taken into account. This paper presents a complete procedure for efficient reduction of realistic, hierarchy aware, EM based parametric models. Knowledge of the structure of the problem is explicitly exploited using domain partitioning and novel electromagnetic connector modeling techniques to generate a hierarchical representation. This enables the efficient use of block parametric model order reduction techniques to generate block-wise compressed models that satisfy overall requirements, and provide accurate approximations of the complete EM behaviour, which are cheap to evaluate and simulate.

Passivity is an important property for a macro-model generated from measured or simulated data. Existence of purely imaginary eigenvalues of a Hamiltonian matrix provides useful information in assessing and correcting the passivity of a system. Since direct computation of eigenvalues is very expensive for large-scale systems, several authors have proposed to solve iteratively for a subset of the eigenvalues based on heuristic sampling along the imaginary axis. However, completeness is not guaranteed in such methods and thus potential risk of missing important eigenvalues is difficult to avoid. In this paper we are aiming at finding all eigenvalues efficiently to avoid both the high cost and the potential risk of missing important eigenvalues. The idea of the proposed method is to convert the Hamiltonian matrix to an equivalent sparse form, termed the "extended Hamiltonian pencil", and solve for its eigenvalues efficiently using a special eigensolver. Experiments on several realistic systems demonstrate an 80X speed-up compared with standard direct eigensolvers.

Power analysis tools are an integral component of any current power sign-off methodology. The performance of a design's power grid affects the timing and functionality of a circuit, directly impacting the overall performance. Ensuring power grid robustness implies taking into account, among others, static and dynamic effects of voltage drop, ground bounce, and electromigration. This type of verification is usually done by simulation, targeting a worst-case scenario where devices, switching almost simultaneously, could impose stern current demands on the power grid. While determination of the exact worst-case switching conditions from the grid perspective is usually not practical, the choice of simulation stimuli has a critical effect on the results of the analysis. Targetting safe but unrealistic settings could lead to pessimistic results and costly overdesigns in terms of die area. In this article we describe a software tool that generates a reasonable, realistic, set of stimuli for simulation. The approach proposed accounts for timing and spatial restrictions that arise from the circuit's netlist and placement and generates an approximation to the worst-case condition. The resulting stimuli indicate that only a fraction of the gates change in any given timing window, leading to a more robust verification methodology, especially in the dynamic case. Generating such stimuli is akin to performing a standard static timing analysis, so the tool fits well within conventional design frameworks. Furthermore, the tool can be used for hotspot detection in early design stages.

Modern deep sub-micron ULSI designs with hundreds of millions of devices require huge grids for power distribution. Such grids, operating with increasingly low-power voltages, are a design limiting factor and accurate analysis of their behavior is of paramount importance as any voltage drops can seriously impact performance or functionality. As power grid models have millions of unknowns, highly optimized special purpose simulation tools are required to handle the time and memory complexity of solving for their dynamic behavior. In this work, we propose a hierarchical matrix representation of the power grid model that is both space and time efficient. With this representation, reduced storage matrix factors are efficiently computed and applied in the analysis at every time-step of the simulation. Results show an almost linear complexity growth, namely O(n loga(n)), for some small constant a, in both space and time, when using this matrix representation. Comparisons of our academic implementation with production-quality code proves this method to be very efficient when dealing with the simulation of large power grid models.

In this paper we describe a flexible and efficient new algorithm for model order reduction of parameterized systems. The method is based on the reformulation of the parametric system as a parallel interconnection of the nominal transfer function and the non-parametric transfer function sensitivities with respect to the parameter variations. Such a formulation reveals an explicit dependence on each parameter which is exploited by reducing each component system independently via a standard non-parametric structure preserving algorithm. Therefore, the resulting smaller size interconnected system retains the structure of the original with respect to parameter dependence. This allows for better accuracy control, enabling independent adaptive order determination with respect to each parameter and adding flexibility in simulation environments. It is shown that the method is efficiently scalable and preserves relevant system properties such as passivity. The new technique can handle fairly large parameter variations on systems whose outputs exhibit smooth dependence on the parameters. Several examples show that besides the added flexibility and control, when compared with competing algorithms, the proposed technique can, in some cases, produce smaller reduced models with potential accuracy gains.

Reduced order modeling is a well-known methodology for linear system modeling. In the past decade it has risen to prominence in the VLSI electronic design area as the de facto standard set of techniques for interconnect and package modeling. With shrinking technologies and faster operating frequencies, such previously ignored structures can have a first order influence in the behavior of many electronic systems. Reduced order modeling techniques can provide accurate, robust, accuracy-controlled models of linear networks. Unfortunately, most of these techniques have difficulty reducing networks with a large number of ports, such as power grids, substrate models and coupled data buses. In this paper we provide a characterization of this problem and discuss the complexity of several previously proposed techniques for handling this problem. We show that for most of these techniques there is little hope to expect that considerable reduction can be achieved. We also show that a simple, perhaps not obvious, approach can theoretically provide better reduction than most of the other techniques.

Analysis and verification environments for next- generation nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects, such as process variations and Electromagnetic (EM) couplings. Designed-in passives, substrate, interconnect and devices can no longer be treated in isolation as the interactions between them are becoming more relevant in the behavior of the complete system. At the same time variations in process parameters lead to small changes in the device characteristics that may directly affect system performance. These two effects, however, can not be treated separately as the process variations that modify the physical parameters of the devices also affect those same EM couplings. Accurately capturing the effects of process variations as well as the relevant EM coupling effects requires detailed models that become very expensive to simulate. Reduction techniques able to handle parametric descriptions of linear systems are necessary in order to obtain better simulation performance. In this work Model Order Reduction techniques able to handle parametric system descriptions are presented. Such techniques are based on Structure-Preserving formulations that are able to exploit the hierarchical system representation of designed- in blocks, substrate and interconnect, in order to obtain more efficient simulation models.

Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation

Multipoint projection methods have gained much notoriety in model-order reduction of linear, nonlinear, and parameter-varying systems. A well-known difficulty with such methods lies in the need for clever point selection to attain model compactness and accuracy. In this paper, the authors present a method for sample point selection in multipoint projection-based model-order reduction. The proposed technique, which is borrowed from the statistical modeling area, is based on resampling schemes to estimate error and can be coupled with recently proposed order reduction schemes to efficiently produce accurate models. Two alternative implementations are presented: 1) a rigorous linear-matrix-inequality-based technique and 2) a simpler, more efficient, heuristic search. The goal of this paper is to answer two questions. First, can this alternative metric be effective in selecting sample points in the sense of placing points in regions of high error without recourse to evaluation of the larger system? Second, if the metric is effective in this sense, under what conditions are substantial improvements in the model reduction efficiency achieved? Results are shown that indicate that the metric is indeed effective in a variety of settings, therefore opening the possibility for performing adaptive error control

This work presents a model reduction algorithm motivated by a connection between frequency-domain projection methods and approximation of truncated balanced realizations. The method is computationally simple to implement, has near-optimal error properties, and possesses simple error estimation and order-control procedures. Usage of the method also enables straightforward exploitation of information about the particular application and setting, as well as circuit functional information, such as frequency weighting information and correlations between network port waveforms. When such specific information is available, standard truncated balanced realization algorithms generate models far from optimal according to statistical decision criteria. Examples are shown to demonstrate that the method can outperform the standard order reduction techniques by providing similar accuracy with lower order models or superior accuracy for the same size model.

In this paper we present a model reduction algorithm that circumvents some of the issues encountered for parasitic networks with large numbers of input/output "ports". Our approach is based on the premise that for such networks, there are typically strong dependencies between the input waveforms at different network "ports". We present an approximate truncated balanced realizations procedure that, by exploiting such correlation information, produces much more compact models compared to standard algorithms such as PRIMA.

This paper presents a model reduction algorithm motivated by a connection between frequency domain projection methods and approximation of truncated balanced realizations. The method produces guaranteed passive models, has near-optimal error properties, is computationally simple to implement, contains error estimators, and can incorporate frequency weighting information in a straightforward manner. Examples are shown to prove that the method can outperform the standard order reduction techniques by providing similar accuracy with lower models or superior accuracy for the same size model.

In this paper, we present a methodology for generating guaranteed passive time-domain models of subsystems described by tabulated frequency-domain data obtained through measurement or through physical simulation. Such descriptions are commonly used to represent on- and off-chip interconnect effects, package parasitics, and passive devices common in high-frequency integrated circuit applications. The approach, which incorporates passivity constraints via convex optimization algorithms, is guaranteed to produce a passive-system model that is optimal in the sense of having minimum error in the frequency band of interest over all models with a prescribed set of system poles. We demonstrate that this algorithm is computationally practical for generating accurate high-order models of data sets representing realistic, complicated multiinput, multioutput systems.

The major concerns in state-of-the-art model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms, such as PRIMA, generate guaranteed-passive models for systems with special internal structure, using numerically stable and efficient Krylov-subspace iterations. Truncated balanced realization (TBR) algorithms, as used to date in the design automation community, can achieve smaller models with better error control, but do not necessarily preserve passivity. In this paper, we show how to construct TBR-like methods that generate guaranteed passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.

The major concerns in state-of-the-art model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms such as PRIMA generate guaranteed-passive models, for systems with special internal structure, using numerically stable and efficient Krylov-subspace iterations. Truncated Balanced Realization (TBR) algorithms, as used to date in the design automation community, can achieve smaller models with better error control, but do not necessarily preserve passivity. In this paper we show how to construct TBR-like methods that guarantee passive reduced models and in addition are applicable to state-space systems with arbitrary internal structure.

As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-speed digital, and microwave systems, it is increasingly important to model previously neglected frequency domain effects. In this paper, results from Nevanlinna-Pick interpolation theory are used to develop a bounded real matrix rational approximation algorithm. A method is presented that allows for the generation of guaranteed passive rational function models of passive systems by approximating their scattering parameter matrices. Since the order of the models may in some cases be high, an incremental fitting strategy is also proposed that allows for the generation of smaller models while still meeting the required passivity and accuracy requirements. Results of the application of the proposed method to several real-world examples are also shown.

Verification of contemporary integrated circuits requires accurate modeling of high-frequency effects in all passive component sub-systems. Often, descriptions of those subsystems are only available in the frequency-domain. In this paper, we propose a simple, scalar, constrained-passive rational approximation scheme that incorporates a grid-based test for strict positive realness. In contrast to similar recent work based on convex optimization and the positive real lemma, the methodology is potentially more efficient, since it does not introduce a quadratic number of auxiliary variables, is potentially more accurate, since pole locations can be re-adjusted during the optimization, but possibly less reliable, since it relies on the solution of optimization problems that are not convex. There-fore, because of the use of local constrained non-convex optimization, the generation of feasible initial guesses is also considered.

The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of instances of Boolean satisfiability. Several path sensitization models and delay models are studied. In addition we evaluate some of the most competitive Boolean satisfiability algorithms seeking to identify which are best suited for solving circuit delay computation problems. Finally, realistic delay modeling (taking into account extracted interconnect delays and fanout data) is considered in order to experimentally evaluate the complexity of solving real-world instances.

Shrinking feature sizes and increasing speeds of operation make interconnect-related effects very relevant for current circuit verification methodologies. Reliable and accurate system verification requires the full analysis of circuits together with the environment that surrounds them, including the common substrate, the packaging structures, and perhaps even board information. In this paper we discuss circuit-level simulation algorithms that enable the analysis of the impact of strongly coupled interconnect structures on nonlinear circuit operation, so as to allow reliable and accurate system verification.

Abstract | The paper proposes an initial benchmark set, suitable for substrate analysis and test. The aim is to help accurately represent electrical noise injected into and picked up from substrate in a variety of high performance circuits. Creating an accurate image of such noise is becoming a critical requirement with the expansion of real plug-and-playstyle designs. Several important methods for the analysis of substrate parasitic coupling are reviewed in light ofthe e ect substrate noise has on the performance of analog and digital ICs over a wide frequency spectrum. The requirements and formats for each benchmark are described in full detail to allow possible algorithmic as well as signal integrity tests. I.

The problem of computing rational function approximations to tabulated frequency data is of paramount importance in the modeling arena.In this paper we present a method for generating a state space model from tabular data in the frequency domain that solves some of the numerical difficulties associated with the traditional fitting techniques used in linear least squares approximations.An extension to the MIMO case is also derived.

Article Interconnect analysis: from 3-D structures to circuit models Share on Authors: M. Kamon Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , N. Marques Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , Y. Massoud Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , L. Silveira Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile , J. White Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 910–914https://doi.org/10.1145/309847.310097Online:01 June 1999Publication History 8citation278DownloadsMetricsTotal Citations8Total Downloads278Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Accurate modeling of noise coupling effects due to crosstalk via the substrate is an increasingly important concern for the design and verification of mixed analog-digital systems. In this paper we present a technique to accelerate the model computation using BEM methods that can be used for accurate and efficient extraction of substrate coupling parameters in mixed-signal designs.

Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.

Industry trends aimed at integrating higher levels of circuit functionality have triggered a proliferation of mixed analog-digital systems. Magnified noise coupling through the common chip substrate has made the design and verification of such systems an increasingly difficult task. In this paper we present a fast eigendecomposition technique that accelerates operator application in BEM methods and avoids the dense-matrix storage while taking all of the substrate boundary effects into account explicitly. This technique can be used for accurate and efficient modeling of substrate coupling effects in mixed-signal integrated circuits.

As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate three-dimensional interconnect models. In this paper, we describe an integral equation aproach to modeling the impedance of inter-connect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior: Our formulation, based on a combination of nodal and mesh analysis, has the required properties to be combined with Model Order Reduction techniques to generate accurate and guaranteed passive low order Interconnect models for efficient inclusion in standard circuit simulators. Furthermore, the formulation is shown to be more flexible and efficient than previously reported methods.

Industry trends aimed at integrating higher levels of circuit functionality have triggered a proliferation of mixed analog-digital systems. Magnified noise coupling through the common chip substrate has made the design and verification of such systems an increasingly difficult task. In this paper we present a fast eigen-decomposition technique that accelerates operator application in BEM methods and avoids the dense-matrix storage while taking all of the substrate boundary effects into account explicitly. This technique can be used for accurate and efficient modeling of substrate coupling effects in mixed-signal integrated circuits.

As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. In this paper we describe an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. Unlike previous methods, our approach is based on a modified nodal analysis formulation and can be used directly to generate guaranteed passive low order interconnect models for efficient inclusion in a standard circuit simulator.

Pade approximation is an often-used method for reducing the order of a finite-dimensional, linear, time invariant, signal model. It is known to suffer from two problems: numerical instability during the computation of the Pade coefficients and lack of guaranteed stability for the resulting reduced model even when the original system is stable. We show how the numerical instability problem can be avoided using the Arnoldi algorithm applied to an appropriately chosen Krylov subspace. Moreover, we give an easily computable sufficient condition on the system matrix that guarantees the stability of the reduced model at any approximation order.

Since the first papers on asymptotic waveform evaluation (AWE), Pade-based reduced order models have become standard for improving coupled circuit-interconnect simulation efficiency. Such models can be accurately computed using bi-orthogonalization algorithms like Pade via Lanczos (PVL), but the resulting Pade approximates can still be unstable even when generated from stable RLC circuits. For certain classes of RC circuits it has been shown that congruence transforms, like the Arnoldi algorithm, can generate guaranteed stable and passive reduced-order models. In this paper we present a computationally efficient model-order reduction technique, the coordinate-transformed Arnoldi algorithm, and show that this method generates arbitrarily accurate and guaranteed stable reduced-order models for RLC circuits. Examples are presented which demonstrates the enhanced stability and efficiency of the new method.

Since the rst papers on asymptotic waveform evaluation (AWE), reduced order models have become standard for improving interconnect simulation eciency, and very recent w ork has demonstrated that bi-orthogonalization algorithms can be used to robustly generate AWE-style macromodels.In this paper we describe using block Arnoldi-based orthogonalization methods to generate reduced order models from FastHenry, a m ultipole-accelerated three dimensional inductance extraction program.Examples are analyzed to demonstrate the eciency and accuracy of the block Arnoldi algorithm.

In this paper we describe an algorithm for ecient circuit-level simulation of transmission lines which can be speci ed by tables of frequency-dependent scattering parameters.The approach uses a forced stable section-by-section `2 minimization approach to construct a high order rational function approximation to the frequency domain data, and then applies guaranteed stable balanced realization techniques to reduce the order of the rational function.The rational function is then incorporated in a circuit simulator using fast recursive convolution.An example of a transmission line with skin-eect is examined to both demonstrate the eectiveness of the approach and to show its generality. 31

This paper presents the algorithms for CMVSIM, a program for performing the transient simulation of grid based analog signal processors on a massively parallel computer. A grid-based equation formulation approach and a block-diagonal preconditioned CGS algorithm are described, and it is shown how they are used to efficiently perform transient simulation using the massively parallel Connection Machine. Experimental results using CMVSIM to simulate realistic image processing circuits are given to demonstrate that the algorithms presented are effective for a general class of grid-based signal processors. In particular, the results presented demonstrate that CMVSIM: running on a full-size Connection Machine can be as much as 650 times faster than what is, to the authors' knowledge, the fastest serial transient simulation algorithm running on a SUN-4/490 workstation.>

The stability and accuracy properties of exponentially fit integration algorithms applied to the test problem x=-Ax are compared with the more standard backward-Euler and semi-implicit methods. For the analysis, A in IR/sup n*n/ is assumed to be connectedly diagonally dominant with positive diagonals, as this models the equations resulting from the way MOS transistors and interconnect parasitics are treated in circuit-level timing simulation programs. Examples are used to demonstrate that all the exponential-fitting methods, and the semi-implicit methods, are much less accurate than backward-Euler for tightly coupled stiff problems, and an example is given which destabilizes one of the exponential-fitting methods. It is then proved that in the limit of large time steps, the more stable exponential-fitting methods become equivalent to a semi-implicit algorithm. It is shown that the backward-Euler, semi-implicit, and certain exponentially fit algorithms are multirate A-stable.>

A modified envelope-following method for simulation of clocked analog circuits is described. The modification makes the envelope-following algorithm more efficient, as unnecessary numerical integration is avoided when computing the envelope of 'quasi-algebraic' components in the solution vector. An automatic method for determining the quasi-algebraic solution components is described, and experimental results are given which demonstrate that this modified method reduces the number of computer clock cycles needed to accurately determine the envelope.>

Specialized algorithms for circuit-level simulation of grid-based analog signal processing arrays on a massively parallel processor are described and implementation results presented. The trapezoidal rule is used to discretize the differential equations that describe the analog array behavior, Newton's method is used to solve the nonlinear equations generated at each time-step, and a block conjugate-gradient squared algorithm is used to solve the linear equations generated by Newton's method. Excellent parallel performance of the algorithm is achieved through the use of a novel, but very natural, mapping of the circuit data onto the massively parallel architecture. The mapping takes advantage of the underlying computer architecture and the structure of the analog array problem. Experimental results demonstrate that a full-size Connection Machine can provide a 1400 times speedup over a SUN-4/280 workstation.>