Partitioning is a fundamental problem in diverse fields of study such as data mining, parallel processing, and the design of VLSI circuits. A new approach to partition graphs and hypergraphs is introduced. This new approach combines local and global sampling, clustering, and Tabu search in a multilevel partitioning algorithm (TPART). TPART was implemented in a C program and compared to many state-of-the-art partitioning algorithms using a wide variety of benchmarks. TPART consistently performs well on the various benchmarks used and in comparison with other partitioning algorithms. TPART has a reasonably fast running time and it can produce a high quality partition of a graph of 262,144 nodes and 524,286 edges in less than 2 minutes CPU times on a Compaq Alpha DS20E 67/667 MHZ machine with 1GB of main memory.

This paper describes a new multi-level partitioning algorithm (PART) that combines a blend of iterative improvement and clustering, biasing of node gains, and local uphill climbs. PART is competitive with recent state-of-the-art partitioning algorithms. PART was able to find new lower cuts for a number of benchmark circuits.

This paper introduces a new algorithm for quickly answering repetitive least-cost queries between pairs of points on the Earth's surface as represented by digital topographical maps. The algorithm uses a three-step process; preprocessing, geometrically modified Dijkstra search, and postprocessing. The preprocessing step computes and saves highly valuable global information that describes the underlying geometry of the terrain. The search step solves shortest path queries using a modified Dijkstra algorithm that takes advantage of the preprocessed information to "jump" quickly across flat terrain and decide whether a path should go over or through a high-cost region. The final step is a path improvement process that straightens and globally improves the path. Our algorithm partitions the search space into free regions and obstacle regions. However, unlike other algorithms using this approach, our algorithm keeps the option of passing through an obstacle region.

Linear placement has several applications in the design of very large scale integrated (VLSI) circuits. Several authors have recently shown that node clustering or compaction enhances the performance of iterative algorithms. This paper describes a technique to extract clusters by means of an algorithm that identifies a maximum weight matching in a path graph in linear time. The resulting linear placement algorithm (CLP) combines node compactions and iterative improvement in an efficient and effective approach. The benefit of compaction is quite visible. Comparisons of the results of CLP with and without compaction on several test cases show the dramatic effect of compaction on the final solution. The approach of CLP is an efficient improvement of the linear placement algorithm of Saab and Chen [1994]. On many instances with known optimal solutions, CLP also achieves an optimal solution. The dependency of the results of CLP on the initial placement is minimal, since solutions found by CLP using many different starts do not significantly differ from each other. Under suitable assumption, CLP can be shown to run in O(nP), where n and P are the number of nodes and the number of pins of the input circuit, respectively.

This paper discusses a new approach for generating test vectors, using test cultivation, for both combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The hierarchical technique used in the analysis drastically reduces the memory requirements, allowing test generation for large circuits. The test cultivation algorithms are simulation-based and a test set can be cultivated for any circuit that can be simulated logically. In particular, general MOS digital designs can be handled, and both stuck-at and transistor faults can be accurately modeled. Using the approach, tests were generated with very high fault coverage for gate-level circuits as well as for transistor level circuits.

Partitioning is a fundamental problem in diverse fields of study such as pattern recognition, parallel processing, and the design of VLSI circuits. Recently, node clustering or compaction has been shown to enhance the performance of iterative partitioning algorithms by several authors. However, clustering has been mainly used as a preprocessing step before partitioning in existing methods. The paper describes a technique to extract clusters using information collected during a pass of an iterative exchange algorithm. Alternative approaches for the implementation of this new clustering technique are discussed, and one such approach is chosen to be incorporated in a modified Fiduccia-Mattheyses algorithm (C.M. Fiduccia, R.M. Mattheyses, 1982) based on a tradeoff between run time and performance. The resulting algorithm, BISECT, performs well in comparison with variants of the Kernighan-Lin algorithm including the Fiduccia-Mattheyses algorithm, local approaches, and simulated annealing on a wide variety of real and randomly generated benchmarks. BISECT is also used to find small vertex separators, and its results are compared with previous methods on several benchmarks. The empirical results show that BISECT is stable and is not very sensitive to the initial partition. Under suitably mild assumptions, BISECT can be shown to run in linear time. The empirical results confirm the speed of BISECT which can partition very large graphs (12,598 nodes and 91,961 edges) in less than six minutes of CPU time on a Sun Sparc 1+ workstation.>

An approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels is discussed. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses a hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handled, and both stuck-at and transistor faults are handled accurately. The approach was implemented in a hierarchical test generation system, CRIS, that runs under UNIX on SPARC workstations. CRIS was used successfully to generate tests with high fault coverage for large combinational and sequential circuits.>

A novel technique is introduced, called stochastic evolution (SE), for solving a wide range of combinatorial optimization problems. It is shown that SE can be specifically tailored to solve the network bisection, traveling salesman, and standard cell placement problems. Experimental results for these problems show that SE can produce better quality solutions than sophisticated simulated annealing (SA)-based heuristics in a much shorter computation time.>

There are two canonical optimization problems, namely, NETWORK BISECTIONING (NB) and TRAVELING SALESMAN (TS), that emerge from the physical design and layout of integrated circuits. In this paper, we use an analogy between iterative techniques for combinatorial optimization and the evolution of biological species to obtain the Stochastic Evolution (SE) heuristic for solving a wide range of combinatorial optimization problems. We show that SE can be specifically tailored to solve both NB and TS. Experimental results for the NB and TS problems show that the SE algorithm produces better quality solutions and is faster than the Simulated Annealing algorithm in all instances considered.

The graph bisectioning problem has several applications in VLSI layout, such as floorplanning and module placement. A sufficient condition for optimality of a given bisection is presented. This condition leads to an algorithm that always finds an optimal bisection for a certain class of graphs. A greedy approach is then used to develop a more powerful heuristic. On small random graphs with up to 20 vertices, one of the greedy algorithms generated the optimal bisection in each case considered. For very large graphs with 300 vertices or more, the algorithm generated bisections with costs within 30% of a lower bound previously derived. An adaptive algorithm that iteratively improves upon a given initial bisection of a graph is presented. Its performance is compared with that of the well-known Kernighan-Lin method on many random graphs with large numbers of vertices. The results indicate that the new adaptive heuristic produces bisections with costs within 2% of those produced by the Kernighan-Lin method (the costs were actually lower in about 70% of the cases) with a three times faster computation speed in most cases.>

In the design of application specific integrated circuits (ASIC), it is often required to partition a logic complex into smaller subcomplexes satisfying a number of constraints. Due to the complexity of the problem, most existing algorithms try to optimize on only one constraint. In this paper, we use the concept of evolution to derive a partitioning algorithm capable of handling a number of constraints. Our algorithm provides a uniform multi-way partitioning scheme, obtains good partitions, and has a fast execution time.