Christof Teuscher

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23ranked-venue papers
8as first author
4since 2021 · last 2026
0000-0002-5927-1900ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 12 · 4 first-author · 3 since 2021Artificial intelligence and machine learning · 9 · 4 first-authorSecurity and privacy · 1Theory of computation · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2026 A Proposed Research Platform for Fully Adiabatic, Reversible, and Superscalar (FARS) Microarchitectures
Byron Gregg, Christof Teuscher
RC2
2022 Guest Editorial: Special Section on Parallel and Distributed Computing Techniques for Non-Von Neumann Technologies
Scott Pakin, Christof Teuscher, Catherine D. Schuman
IEEE Trans. Parallel Distributed Syst.2
2021 A golden age for computing frontiers, a dark age for computing education?
abstract
There is no doubt that the body of knowledge spanned by the computing disciplines has gone through an unprecedented expansion, both in depth and breadth, over the last century. In this position paper, we argue that this expansion has led to a crisis in computing education: quite literally the vast majority of the topics of interest of this conference are not taught at the undergraduate level and most graduate courses will only scratch the surface of a few selected topics. But alas, industry is increasingly expecting students to be familiar with emerging topics, such as neuromorphic, probabilistic, and quantum computing, AI, and deep learning. We provide evidence for the rapid growth of emerging topics, highlight the decline of traditional areas, muse about the failure of higher education to adapt quickly, and delineate possible ways to avert the crisis by looking at how the field of physics dealt with significant expansions over the last centuries.
Christof Teuscher
CF1
2021 Computational Capacity of Complex Memcapacitive Networks
abstract
Emerging memcapacitive nanoscale devices have the potential to perform computations in new ways. In this article, we systematically study, to the best of our knowledge for the first time, the computational capacity of complex memcapacitive networks, which function as reservoirs inreservoir computing,one of the brain-inspired computing architectures. Memcapacitive networks are composed of memcapacitive devices randomly connected through nanowires. Previous studies have shown that both regular and random reservoirs provide sufficient dynamics to perform simple tasks. How do complex memcapacitive networks illustrate their computational capability, and what are the topological structures of memcapacitive networks that solve complex tasks with efficiency? Studies show that small-world power-law (SWPL) networks offer an ideal trade-off between the communication properties and the wiring cost of networks. In this study, we illustrate the computing nature of SWPL memcapacitive reservoirs by exploring the two essential properties: fading memory and linear separation through measurements of kernel quality. Compared to ideal reservoirs, nanowire memcapacitive reservoirs had a better dynamic response and improved their performance by 4.67% on three tasks: MNIST, Isolated Spoken Digits, and CIFAR-10. On the same three tasks, compared to memristive reservoirs, nanowire memcapacitive reservoirs achieved comparable performance with much less power, on average, about 99× , 17×, and 277×, respectively. Simulation results of the topological transformation of memcapacitive networks reveal that that topological structures of the memcapacitive SWPL reservoirs did not affect their performance but significantly contributed to the wiring cost and the power consumption of the systems. The minimum trade-off between the wiring cost and the power consumption occurred at different network settings ofαandβ: 4.5 and 0.61 forBiolekreservoirs, 2.7 and 1.0 forMohamedreservoirs, and 3.0 and 1.0 forNajemreservoirs. The results of our research illustrate the computational capacity of complex memcapacitive networks as reservoirs in reservoir computing. Such memcapacitive networks with an SWPL topology are energy-efficient systems that are suitable for low-power applications such as mobile devices and the Internet of Things.
Christof Teuscher
ACM J. Emerg. Technol. Comput. Syst.2
2020 Impact of Memristor Defects in a Neuromorphic Radionuclide Identification System
abstract
Memristor arrays are promising structures for energy-efficient neuromorphic computing systems. However, due to their nondeterministic fabrication process, manufacturing defects can degrade computation accuracy. In this paper, a memristor-based neuromorphic radionuclide identification system is proposed and tested for robustness. The computational task consists of classifying an incoming radionuclide signal from a dictionary of well-known radionuclides. Nuclide identification accuracy was determined by performing a defect-oriented testing of the system. Defect analysis and modelling focused on static faults, where the memristor resistivity was stuck at extreme values. Results show that the system has a higher tolerance to static defects where the resistance is jammed at the maximum extreme (effective open circuit) than in the minimum extreme (effective short circuit). It is shown that the system maintains close to its full performance when up to 15% random open defects are present in the array. The outcomes of this work are relevant to implementing state-of-the-art memristive devices into similar neuromorphic computing systems.
Jorge I. Canales-Verdial, Walt Woods, Christof Teuscher, Marek Osinski, Payman Zarkesh-Ha
ISCAS3
2020 Approximate Memristive In-Memory Hamming Distance Circuit
abstract
Hamming Distance (HD) is a popular similarity measure that is used widely in pattern matching applications, DNA sequencing, and binary error-correcting codes. In this article, we extend our previous work to prove that our HD circuit is scalable, tolerant to memristor model variability, and tolerant to device-to-device variation. We showed that the operation of our circuit under non-ideal fabrication conditions changes slightly, decreasing the correct classification rates for the MNIST handwritten digits dataset by <1%. Our circuit’s operation is independent of the memristor model used, as long as the model allows a reverse current. Because we leverage in-memory parallel computing, our circuit is n × faster than other HD circuits, where n is the number of HDs to be computed, and it consumes ≈100× − 1,000× less power compared to other memristive and CMOS HD circuits. Used in a full HD Associative Content Addressable Memory (ACAM), the proposed HD circuit consumes only 2.2% of the total system power. Our state-of-the-art, low-power, and fast HD circuit is relevant for a wide range of applications.
Mohammad Mahmoud A. Taha, Christof Teuscher
ACM J. Emerg. Technol. Comput. Syst.2
2019 Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture
abstract
Memristive crossbars have become a popular means for realizing unsupervised and supervised learning techniques. In previous neuromorphic architectures with leaky integrate-and-fire neurons, the crossbar itself has been separated from the neuron capacitors to preserve mathematical rigor. In this paper, we sought to design a simplified sparse coding circuit without this restriction, resulting in a fast circuit that approximated a sparse coding operation at a minimal loss in accuracy. We showed that connecting the neurons directly to the crossbar resulted in a more energy-efficient sparse coding architecture and alleviated the need to prenormalize receptive fields. This paper provides derivations for the design of such a network, named the simple spiking locally competitive algorithm, as well as CMOS designs and results on the CIFAR and MNIST data sets. Compared to a nonspiking, nonapproximate model which scored 33% on CIFAR-10 with a single-layer classifier, this hardware scored 32% accuracy. When used with a state-of-the-art deep learning classifier, the nonspiking model achieved 82% and our simplified, spiking model achieved 80% while compressing the input data by 92%. Compared to a previously proposed spiking model, our proposed hardware consumed 99% less energy to do the same work at 21 × the throughput. Accuracy held out with online learning to a write variance of 3%, suitable for the often reported 4-bit resolution required for neuromorphic algorithms, with offline learning to a write variance of 27%, and with read variance to 40%. The proposed architecture's excellent accuracy, throughput, and significantly lower energy usage demonstrate the utility of our innovations.
Walt Woods, Christof Teuscher
IEEE Trans. Neural Networks Learn. Syst.2
2017 Feedforward Chemical Neural Network: An In Silico Chemical System That Learns xor
abstract
Inspired by natural biochemicals that perform complex information processing within living cells, we design and simulate a chemically implemented feedforward neural network, which learns by a novel chemical-reaction-based analogue of backpropagation. Our network is implemented in a simulated chemical system, where individual neurons are separated from each other by semipermeable cell-like membranes. Our compartmentalized, modular design allows a variety of network topologies to be constructed from the same building blocks. This brings us towards general-purpose, adaptive learning in chemico: wet machine learning in an embodied dynamical system.
Drew Blount, Peter Banda, Christof Teuscher, Darko Stefanovic
Artif. Life3
2014 An Analog Chemical Circuit with Parallel-Accessible Delay Line for Learning Temporal Tasks
abstract
peer reviewed
Peter Banda, Christof Teuscher
ALIFE2
2014 Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip
abstract
Traditional metal-wire-based networks-on-chip (NoC) suffer from high latency and power dissipation as the system size scales up in the number of cores. This limitation stems from the inherent multihop communication nature of larger NoCs. It has previously been shown that the performance of NoCs can be significantly improved by introducing long-range, low power, and high-bandwidth single-hop links between distant cores. While previous work has focused on specific NoC architectures and configurations, it remains an open question whether heterogeneous link types are beneficial in a broad range of NoC architectures. In this article, we show that a generic NoC architecture with heterogeneous link types allows for NoCs with higher bandwidth at a lower cost compared to homogeneous networks. We further show that such NoCs scale up significantly better in terms of performance and cost. We demonstrate these broadly-applicable results by using a technology-agnostic complex network approach that targets NoC architectures with various emerging link types.
Haera Chung, Christof Teuscher, Partha Pratim Pande
ACM J. Emerg. Technol. Comput. Syst.2
2013 Online Learning in a Chemical Perceptron
abstract
Autonomous learning implemented purely by means of a synthetic chemical system has not been previously realized. Learning promotes reusability and minimizes the system design to simple input-output specification. In this article we introduce a chemical perceptron, the first full-featured implementation of a perceptron in an artificial (simulated) chemistry. A perceptron is the simplest system capable of learning, inspired by the functioning of a biological neuron. Our artificial chemistry is deterministic and discrete-time, and follows Michaelis-Menten kinetics. We present two models, the weight-loop perceptron and the weight-race perceptron, which represent two possible strategies for a chemical implementation of linear integration and threshold. Both chemical perceptrons can successfully identify all 14 linearly separable two-input logic functions and maintain high robustness against rate-constant perturbations. We suggest that DNA strand displacement could, in principle, provide an implementation substrate for our model, allowing the chemical perceptron to perform reusable, programmable, and adaptable wet biochemical computing.
Peter Banda, Christof Teuscher, Matthew R. Lakin
Artif. Life2
2012 Finding Optimal Random Boolean Networks for Reservoir Computing
abstract
Reservoir Computing (RC) is a computational model in which a trained readout layer interprets the dynamics of a component called a reservoir that is excited by external input stimuli. The reservoir is often constructed using homogeneous neural networks in which a neuron’s in-degree distributions as well as its functions are uniform. RC lends itself to computing with physical and biological systems. However, most such systems are not homogeneous. In this paper, we use Random Boolean Networks (RBN) to build the reservoir. We explore the computational capabilities of such a RC device using the temporal parity task and the temporal density classification. We study the sufficient dynamics of RBNs using kernel quality and generalization rank measures. We verify findings by Lizier et al. (2008) that the critical connectivity of RBNs optimizes the balance between the high memory capacity of RBNs with 〈K 〉 < 2 and the higher information processing of RBNs with 〈K 〉> 2. We show that in a RBN-based RC system, the optimal connectivity for the parity task, a processing intensive task, and the density classification task, a memory intensive task, agree with Lizier et al.’s theoretical results. Our findings may contribute to the development of optimal selfassembled nanoelectronic computer architectures and biologically-inspired computing paradigms.
David R. Snyder, Alireza Goudarzi, Christof Teuscher
ALIFE3
2011 Challenges and promises of nano and bio communication networks
abstract
In recent years, the importance of interconnects on top-down engineered lithography-based electronic chips has outrun the importance of transistors as a dominant factor of performance. The major challenges in traditional chips are related to delays of non-scalable global interconnects and reliability in general, which leads to the observation that simple scaling will no longer satisfy performance requirements as feature sizes continue to shrink. In addition, the advent of massive-scale multicore architectures, novel silicon and non-silicon manufacturing techniques (such as self-assembly), and an increasing interest in biological components for computing force us to rethink, re-evaluate, and re-design the communication infrastructure and the communication paradigms in the era of nano- and biotechnology.
Christof Teuscher, Cristian Grecu, Ron Weiss
NOCS1
2011 Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
abstract
Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.
Amlan Ganguly, Kevin Chang 0002, Sujay Deb, Partha Pratim Pande, Benjamin Belzer, Christof Teuscher
IEEE Trans. Computers6
2008 Non-traditional irregular interconnects for massive scale SoC
abstract
By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way that involve massive numbers of interconnected components. However, such assemblies are often highly irregular, unreliable, and heterogeneous. A grand challenge for future and emerging electronics is thus to reliably and efficiently compute and communicate in such systems. The goal of this paper is to illustrate why non-traditional network-on-chip paradigms are promising for massive scale systems and what the limits are. We have previously shown that certain irregular 3D assemblies and interconnects have major advantages over regular 2D and 3D mesh fabrics in terms of latency, throughput, scalability, and the robustness against simple link failures. We present these results from a complex network perspective and look into the scaling properties of different interconnect topologies and routing algorithms in an abstract framework. We argue that only small-world topologies will scale up to massive scale systems. The long term goal in using irregular, fabrication-friendly, and non-traditional interconnects is to eventually be able to cheaply and easily assemble massive scale computing devices that are able to solve specific large- scale problems competitively with traditional top-down fabricated silicon technology.
Christof Teuscher, Anders A. Hansson
ISCAS1
2007 Exploring Logic Artificial Chemistries: An Illogical Attempt?
abstract
Robustness to a wide variety of negative factors and the ability to self-repair is an inherent and natural characteristic of all life forms on earth. As opposed to nature, man-made systems are in most cases not inherently robust and a significant effort has to be made in order to make them resistant against failures. This can be done in a wide variety of ways and on various system levels. In the field of digital systems, for example, techniques such as triple modular redundancy (TMR) are frequently used, which results in a considerable hardware overhead. Biologically-inspired computing by means of biochemical metaphors offers alternative paradigms, which need to be explored and evaluated. Here, we are interested to evaluate the potential of nature-inspired artificial chemistries and membrane systems as an alternative information representing and processing paradigm in order to obtain robust and spatially extended Boolean computing systems in a distributed environment. We investigate conceptual approaches inspired by artificial chemistries and membrane systems and compare proof-of-concepts. First, we show, that elementary logical functions can be implemented. Second, we illustrate how they can be made more robust and how they can be assembled to larger-scale systems. Finally, we discuss the implications for and paths to possible genuine implementations. Compared to the main body of work in artificial chemistries, we take a very pragmatic and implementation-oriented approach and are interested in realizing Boolean computations only. The results emphasize that artificial chemistries can be used to implement Boolean logic in a spatially extended and distributed environment and can also be made highly robust, but at a significant price
Christof Teuscher
ALIFE1
2007 To each his own: The caregiver's role in a computational model of gaze following
Christof Teuscher, Jochen Triesch
Neurocomputing1
2007 FPGA Implementations of Neural Networks (Ormondi. A.R. and Rajapakse, J.C., Eds.; 2006)
abstract
This timely collection of 12 selected contributions offers exactly what was missing in the exciting and growing area of FPGA-based neurocomputing: an introduction for wannabes and a reference for diehards. The introductory chapter provides a very nice and down-to-earth introduction to all key aspects - from neural network basics to performance evaluation - of FPGA neurocomputers. The rest of the book then covers three main topics: foundation issues, implementations, and the lessons learned from a large scale project. The book has some minor problems with graphics and typesetting, as well as some examples of poor English. It also lacks an index. But problems aside, the volume provides a unique and comprehensive overview on the field that researchers, engineers, and students will certainly find most useful.
Christof Teuscher
IEEE Trans. Neural Networks1
2006 The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability
abstract
In this abstract, the authors present an overview of a reliability analysis toolset, called the scalable tool for the analysis of reliable systems (STAR systems), with modules for determining the reliability of FPGA designs (STAR-circuits) and reconfigurable supercomputers (STAR-reconfigurable supercomputers
Heather M. Quinn, Debayan Bhaduri, Christof Teuscher, Paul S. Graham, Maya B. Gokhale
FCCM3
2001 Self-Organizing Topology Evolution of Turing Neural Networks
Christof Teuscher, Eduardo Sanchez
ICANN1
2000 A Networked FPGA-Based Hardware Implementation of a Neural Network Application
abstract
Describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, an artificial neural network (ANN) that dynamically adapts its size. Most ANN models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices are very well adapted for the implementation of ANNs with in-circuit structure adaptation. To realize this implementation, we used a network of Labomat-3 boards (a reconfigurable platform developed in our laboratory), which communicate with each other using TCP/IP or a faster direct hardware connection.
Héctor Fabio Restrepo, Ralph Hoffmann, Andrés Pérez-Uribe, Christof Teuscher, Eduardo Sanchez
FCCM4
1999 CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor
Emeka Mosanya, Christof Teuscher, Héctor Fabio Restrepo, Patrick Galley, Eduardo Sanchez
CHES2
1999 A Reconfigurable Platform for Academic Purposes
abstract
Labomat 3 is a reconfigurable platform for teaching and research purposes developed by our laboratory. The main features of the board are: (1) a microprocessor associated with two mid-range FPGAs, (2) a powerful multitasking real-time operating system including a JavaVM, (3) easy to use design tools, and (4) a networking interface. In this paper we describe the hardware and software of the board as well as some application domains.
Christof Teuscher, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Eduardo Sanchez, Francisco J. Gomez-Arribas
FCCM1