Heterogeneous systems featuring multiple kinds of processors are becoming increasingly attractive due to their high performance and energy saving over the homogeneous systems. With the OpenCL as a unified programming language providing programs portability, and the recent advances in transistor technology allowing multi-core CPUs, GPUs and FPGA to be on the same chip, finding the best task-to-device mapping will be the key to gain such high performance and leverage their use from application dedicated devices to platforms for concurrent user applications. This work proposes an energy-efficient scheduling scheme to schedule concurrent OpenCl tasks targeting CPU+GPU+FPGA heterogeneous systems by setting the best kernel-device pair at run-time. The scheme is expected to provide the best mapping in terms of throughput and energy consumption under the constraints of hardware resources, concurrent execution and contention scenarios.

This paper presents the hardware implementation (both ASIC and FPGA) of a fuzzy logic-based adaptive routing scheme for Network-on-Chip (NoC). The routing scheme takes into account the dynamic traffic load and power consumption on neighboring router links to select the output port of an incoming flit. Specifically, fuzzy logic control is used to build a simple, generic, and efficient nonlinear control law that dynamically calculates the input link cost. Basing the link cost on traffic load and power consumption and not on empty buffer slots, makes the proposed algorithm applicable to both buffered and bufferless NoCs. Hardware implementation in ASIC and FPGA technologies demonstrate that the hardware area overhead imposed by the fuzzy control logic is from minimal to negligible for practical flit sizes and scales excellently with network size. Furthermore, since the fuzzy control logic is not in the router critical path, it imposes no additional latency. Finally, we demonstrate the efficiency of the proposed routing scheme through simulative evaluation against representative conventional counterparts.

FPGA architecture characteristics and capabilities changed and improved significantly the last years, from a homogeneous and regular architecture to a heterogeneous (or piece-wise homogeneous) and piece-wise regular architecture. The platform-based design allows to designer to build a customized FPGA architecture, using specific blocks, depending on the application domain requirements. Due to the fact that about 70-90% of typical an FPGA is occupied by routing resources, many researchers have spent much effort on minimizing energy consumption and on achieving higher frequencies. Their clear message was the fact that the interconnection structure dominates the total power dissipation and performance. A typical interconnection network of FPGA consists of the Switch Boxes (SBs) and the wire segments. In this paper, we propose a novel methodology for designing a high-performance and low-energy routing architecture of an island style-based FPGA platform. The basic idea behind the new methodology is to choose the corresponding performance and energy efficient combination of multiple SBs and the appropriate wire segment, taking into account the considered application-domain characteristics. More specifically, the proposed methodology selects the appropriate combination of SBs, depending on the localized performance and energy consumption requirements of each specific region of FPGA architecture. The efficiency of an SB and wire segment is characterized by analyzing parameters such as performance, energy dissipation and the number of required tracks for successful application routing. Using MCNC benchmarks, extensive comparison study proves the effectiveness of the proposed approach achieving performance increase of 52% and reduction of energy consumption 12%, in average.

The novel design of an efficient FPGA interconnection architecture with multiple switch boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP applications), is introduced. For that purpose, after exhaustive exploration, we modify the routing architecture through efficient selection of the appropriate switch box with hardwired connections, taking into account the statistical and spatial routing restrictions of DSP applications mapped onto FPGA. More specifically, we propose a new technique for selecting the appropriate combination of switch boxes, depending on the localized performance and power consumption requirements of each specific region of FPGA architecture. In order to perform the mapping, we developed a novel algorithm, which takes into account the modified architectural routing features. This algorithm was implemented within a new tool called EX-VPR. Using a number of DSP applications, extensive comparison study of various combinations of switch boxes in terms of total power consumption, performance, Powerx Delay product prove the effectiveness of the proposed approach.

The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18μm STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems.

In this paper, the EX-VPR tool, which used for architecture level exploration, is presented. This tool belongs to an integrated framework (MEANDER) for mapping applications into a fine-grain reconfigurable platform (FPGA). Having as input VHDL description of an application, the framework produces the appropriate configuration bitstream. The proposed tool framework supports a variety of FPGA architectures. Additionally, a novel power aware switch box is proposed. Quantitative comparisons with existing switch boxes are provided, yielding promising results.

Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

A methodology for power optimization of the data memory hierarchy and instruction memory, is introduced. The effect of the methodology on a set of widely used multimedia application kernels, namely full search, hierarchical search, and parallel hierarchical one dimension search, is demonstrated. Three different target architecture models are used. The issues of the data memory power reduction and instruction memory are tackled separately. We find the power optimal data memory hierarchy applying the appropriate data-use transformation, while the instruction power optimization is done using suitable cache memory. Using data-reuse transformations, performance optimization techniques, and instruction-level transformations, we perform exhaustive exploration of all the possible alternatives to reach power efficient solutions. The experimental results prove the efficiency of the methodology in terms of power for all the multimedia kernels.

A comparison study of four blocking matching algorithms is presented in terms of performance, energy consumption and area, assuming five matching criteria. Two widely-used programmable processor cores, namely the embedded processor, ARM, with specialized memory hierarchy and the general purpose processor, Pentium/sup /spl copy//, are chosen for performing the comparative study, and eventually, determining the most efficient solution for certain design specifications. Adopting a systematic design methodology, efficient high-level transformations are applied to the considered algorithm structures resulting in performance-, energy-, and area-optimized solutions The plethora of alternative implementations under the different distance criteria and processor cores, offers flexibility to the designer in finding the most suitable solution for him/her, given the design specifications.