Autonomous vehicles (AVs) use complex suites of sensors to understand the surrounding environment and inform decision making systems which ensure the efficiency and safety of their operation. Light Detection and Ranging (LiDAR) sensors are an important part of the perception subsystems of many AVs, and are responsible for identifying obstacles to prevent collisions. This critical function makes LiDAR sensors a prime target for malicious attacks such as object hiding attacks in which an attacker uses a laser to spoof a LiDAR point cloud to cause an object to be “hidden” from the AV. However, despite many AVs today having multiple LiDAR sensors with overlapping fields of view, LiDAR spoofing attacks described in existing literature test only on single LiDAR systems. We hypothesize that sensor redundancy can effectively "fill-in" spoofed regions if one of the sensors is attacked, providing some inherent resilience to object hiding attacks. In this work, we evaluate the effectiveness of two object hiding attacks, the Object Removal Attack (ORA) and the Physical Removal Attack (PRA), on an AV digital twin with one, two, and three LiDAR configurations. We report up to an 83% reduction in attack success rate when using multi-LiDAR configurations for both ORA and PRA when hiding vehicles and up to a 100% and 75% reduction for ORA and PRA, respectively, when hiding pedestrians.

The growing number of security threats and vulnerabilities in automotive and industrial control systems motivates the design of Controller Area Network (CAN) bus components with enhanced security measures while maintaining compatibility with existing standards and allowing for interoperability with non-enhanced systems. We present such an enhancement that is implemented by replacing standard CAN bus transceivers with a new transceiver that permits automatic authentication of CAN frames. The theoretical basis of our approach is based on incorporating a secondary communications channel in a virtual manner that simultaneously transmits an authentication signature with each CAN frame. To implement the authentication mechanism, a new backward-compatible transceiver is described, designed and validated that implements the virtual channel through selectively delaying the rising edges in a Non-Return-to-Zero (NRZ) waveform that encodes a CAN frame at the physical layer. Novel aspects of the CAN transceiver include the use of use of authentication signature generators and comparators, rising edge time-based modulator/demodulator circuitry, and phase-preserving rail converters. The mixed-signal transceiver circuit was fabricated using a$0.18\mu $m CMOS process and operation was validated over PVT corner cases and with non-secure transceivers to demonstrate backward compatibility.

We introduce a differentiable statistical moment aggregation layer, enabling networks to learn the optimal method of statistical moment pooling for automatic modulation classification. Statistical pooling, a cornerstone of convolutional networks, consolidates activations into fixed-length representations. Traditionally, this entails mean, variance, and higher-ordered statistics pooling defined as fixed hyperparameters. By enabling the statistics layer to become differentiable, networks are able to optimize the method of statistical aggregations, transcending predefined hyperparameters. With our approach, the statistical moment order is differentiable. Our results demonstrate learned statistical moments are able to outperform fixed-moments—improving modulation classification performance of a time-domain signal.1

Virtualization and cloud computing have become critical parts of modern enterprise computing infrastructure. One of the benefits of using cloud infrastructure over in-house computing infrastructure is the offloading of security responsibilities. By hosting one’s services on the cloud, the responsibility for the security of the infrastructure is transferred to a trusted third party. As such, security of customer data in cloud environments is of critical importance. Side channels and covert channels have proven to be dangerous avenues for the leakage of sensitive information from computing systems. In this work, we propose and perform two experiments to investigate side and covert channel possibilities in virtual, enterprise environments. The first experiment is centered around the use of sensor data available via Intelligent Platform Management Interface, an open standard for out-of-band management often shipped with enterprise-level servers. We show how power-related sensors available with minimal user privilege over IPMI can be correlated with the levels of CPU stress of a virtual machine on a server. This leads to our second experiment, in which we demonstrate a power analysis approach for establishing a covert channel for the exfiltration of data from a network-isolated virtual machine on a server rack. By applying the concept of power analysis more broadly to the power consumption of an entire server rack, rather than individual hardware components, we find that basic patterns in system load can be clearly identified using signal processing techniques, demonstrating the potential for establishing a covert channel.

A new CAN bus transceiver integrated circuit is described that incorporates an inherent auxiliary data channel. The auxiliary data channel enables CAN packet authentication signatures to accompany primary data payloads. The transceiver is backward compatible with the CAN protocol and thus may be used within existing networks with no modifications required. The clock edge at the transmitter is phase modulated with signature data in a manner that does not exceed clock jitter tolerances in the CAN specifications. The receiver is designed to recover the primary data and the packet signature. By comparing the received signature with the authorized packet signature, a “Go/No Go” output indicates if the received packet is properly authenticated.

An overview of the quantum computing paradigm with a focus on reliability is provided in a tutorial form intended for practitioners and researchers in the test and reliability community. It is assumed that readers have little prior knowledge of quantum informatics. An introductory description of the mathematical models of a qubit and quantum information processing operations and projective measurement is presented as background. Discussions of quantum error sources and associated fault models are included using the concepts and notation explained in the background section. Topics related to the decoherence problem are also included. The concept of a logical qubit and how quantum error detection and correction can be applied to enhance reliability of quantum computations is formulated using the notions of classical fault models and error detection and correction techniques. The general concept of quantum error detection and correction as applied to enhancing quantum computational reliability is discussed including an example of one of the first such methods originally introduced in 1995.

Quantum information processing and communication techniques rely heavily upon entangled quantum states, and this dependence motivates the development of methods and systems to generate entanglement. Much research has been dedicated to state preparation for radix-2 qubits, and due to the pursuit of entangled states, the Bell state generator and its generalized forms where the number of entangled qubits is greater than two have been defined. In this work, we move beyond radix-2 and propose techniques for quantum state entanglement in high-dimensional systems through the generalization of the binary bipartite entanglement states. These higher-radix quantum informatic systems are composed of n quantum digits, or qudits, that are each mathematically characterized as elements of an r -dimensioned Hilbert vector space where r > 2. Consequently, the wave function is a time-dependent state vector of dimension r n . The generalization of the binary controlled-NOT to the controlled-modulo-addition gate, the concept of partial versus maximal entanglement, and architectures for generating higher-radix entangled states for the partial and maximal case are all presented.

In this article, an asynchronous serial transceiver that is capable of transmitting and receiving an auxiliary data stream concurrently with the primary data stream is described. The transceiver instantiates the auxiliary data stream by modulating the phase of the primary data without affecting the primary channel transmission and recovery mechanisms. Standard receiver interoperability is maintained since the auxiliary data appear as primary data jitter. Analysis of the proposed transceiver and considerations of the system parameters are included and can be used to determine how such an auxiliary channel is implemented. The proposed transceiver with the auxiliary channel can be widely used in many data communication applications such as for transmitting signatures for authentication or other control information, steganography, or additional data in an existing serial link. A prototype transceiver, implemented in a 65-nm CMOS process, demonstrates the proposed concept with an 80-Mb/s auxiliary channel in a 2.56-Gb/s asynchronous serial link.

Quantum computing, once just a theoretical field, is quickly advancing as physical quantum technology increases in size, capability, and reliability. In order to fully harness the power of a general quantum computer or an application-specific device, compilers and tools must be developed that optimize specifications and map them to a realization on a specific architecture. In this work, a technique and prototype tool for synthesizing algorithms into a quantum computer is described and evaluated. Most recently reported methods produce technologically-independent reversible cascades comprised of a functionally complete set of operators with no regard to actual technologically-dependent cell libraries or constraints due to a device's pre-configured interconnectivity. In contrast, our prototype tool synthesizes algorithms into technologically-dependent specifications that consist of a set of primitives and connectivity constraints present in the computer architecture. The tool performs optimizations based on actual architectural constraints, and a high-quality technology-dependent synthesized result is achieved through the use of optimizing cost functions derived from real hardware and architecture parameters. Additionally, another important aspect of our tool is the incorporation of internal formal equivalence checking that ensures the initially specified algorithm is functionally equivalent to the optimized, technologically-mapped output. Experimental results are provided that target the IBM Q family of quantum computers.

We propose a novel demographic group prediction mechanism for smart device users based upon the recognition of user gestures. The core idea of our proposed approach is to utilize data from a variety of the internal environmental sensors in the device to predict useful demographics information. In order to achieve this objective, an application with several intuitive user interfaces was implemented and used to capture user data. The results presented here are based upon the data from fifty users. These captured data are integrated or fused, pre-processed, analyzed, and used as training data for a supervised machine learning predictive approach. The data reduction methods are based upon principal component analysis (PCA) and linear discriminant analysis (LDA). PCA/LDA were implemented to reduce the data feature dimensions and to improve the k-nearest neighbors (KNN) supervised classification predictions. The results of our experiment indicate that high accuracy is achieved from this method. To the best of our knowledge, this is the first research that uses user recognition gestures to predict multiple demographic groups.

A transfer function is a mathematical function relating the output or response of a system to the input or stimulus. It is a concise mathematical model representing the input/output behavior of a system and is widely used in many areas of engineering including system theory and signal analysis. Binary Decision Diagrams (BDDs) are a canonical representation of Boolean functions. We implement a framework to build transfer function models of digital switching functions using BDDs and demonstrate their application on simulation and implication.

Quantum mechanical phenomena such as phase shifts, superposition, and entanglement show promise in use for computation. Suitable technologies for the modeling and design of quantum computers and other information processing techniques that exploit quantum mechanical principles are in the range of vision. Quantum algorithms that significantly speed up the process of solving several important computation problems have been proposed in the past. The most common representation of quantum mechanical phenomena are transformation matrices. However, the transformation matrices grow exponentially with the size of a quantum system and, thus, pose significant challenges for efficient representation and manipulation of quantum functionality. In order to address this problem, first approaches for the representation of quantum systems in terms of decision diagrams have been proposed. One very promising approach is given by Quantum Multiple-Valued Decision Diagrams (QMDDs) which are able to efficiently represent transformation matrices and also inherently support multiple-valued basis states offered by many physical quantum systems. However, the initial proposal of QMDDs was lacking in a formal basis and did not allow, e.g., the change of the variable order-an established core functionality in decision diagrams which is crucial for determining more compact representations. Because of this, the full potential of QMDDs or decision diagrams for quantum functionality in general has not been fully exploited yet. In this paper, we present a refined definition of QMDDs for the general quantum case. Furthermore, we provide significantly improved computational methods for their use and manipulation and show that the resulting representation satisfies important criteria for a decision diagram, i.e., compactness and canonicity. An experimental evaluation confirms the efficiency of QMDDs.

Interacting with smart devices is a common experience and is becoming an integral part of daily life for many people. Modern smart devices are equipped with a large variety of environmental and user input sensors. We hypothesize that a fusion of smart device sensor data can provide biometric data that allows for classification of user demographics such as age, gender, and native language. A smart device is instrumented with sensor data collection software and with user demographic classification software. An experiment is devised where data is collected for a sample group of users. The data is analyzed, and two classification algorithms are implemented based on the fusion of the different sensors. The classification methods are based upon decision tree and principle component analysis. The results of the experiment indicate that high accuracy is achieved for user demographic classification. Finally, we further discuss the applications and limitations of the study's approach.

Transfer functions are concise mathematical models representing the input/output behavior of a system and are widely used in many areas of engineering including system theory and signal analysis. We develop a framework for the construction of transfer function models for digital networks and demonstrate their application in simulation and implication. Rather than using a traditional switching theory model, the transfer functions are defined over vector spaces, H. The derivation of the transfer function is provided and it is applied to logic network simulation and implication.

The audience will discuss the current state of the effort to update the 2004 document titled "Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering," also known as CE2004. The presenters represent the ACM and the IEEE Computer Society (IEEE-CS), which are leading the effort. They will engage participants on ways of improving the body of knowledge so that the document reflects the state-of-the-art of computer engineering education and practice that is relevant for the coming decade.

Participants of this pre-conference workshop will learn about the development of computer engineering curricula reports. They will also learn about the revision process and will have the opportunity to provide comment and opinion on drafting an update of the joint ACM and IEEE Computer Society document from 2004 titled, “Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering” known also as CE2004. The authors of this workshop welcome all participation including overall comments and targeted editing assistance from the computer engineering education community. This activity will ensure that an updated document is a forward-looking summary of state-of-the-art educational practices in the computer engineering field.

Embedded Systems design courses are important components in software, computer, and electrical engineering programs and curricula. We describe topics for inclusion in these courses and associated hands-on experiences as required portions of the courses including example development systems based upon two popular microcontrollers. We also describe the challenges of offering these courses in distance format and provide examples of how the hands-on component may be included for distance students.

In early 2011, the ACM and the IEEE Computer Society (IEEE/CS) created the CE2004 Review Task Force (RTF) and charged it with the task of reviewing and determining the extent to which the document "Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering," produced 2004 December 12 and known as CE2004 [1] required revisions. The RTF submitted a report to both societies in July of 2011. The report summarized a survey of academic and industry constituents conducted by the RTF. It recommended keeping the structure and the vast majority of the content of the original CE2004 document. However, it also recommended that contemporary topics should be strengthened or added while de-emphasizing other topics that appeared to be waning from the curricular mainstream of computer engineering. Additionally, the RTF recommended that the two societies form a joint special-purpose committee to update and edit the earlier document and to seek input and review from the computer engineering industrial and academic communities through presentations and workshops co-located at major conferences. The presenters of this special session were members of the 2011 RTF and two presenters were members of the original curricular task force from 2004. The presentation will provide insights in the RTF findings and thoughts on how a future computer engineering report might evolve.

An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications including use in computer graphics, digital radio modules, implementation of division and function approximation in ALU circuits. The theory of operation of the circuit is described including radix-4 operand dual recoding. Our recoding yields non negative partial squares and other features which simplify the design of the approximate squaring circuit. Results of the implementation in terms of delay, power, and area in both 130 nm and 90 nm technologies are presented and analyzed. The results show the circuit is power, area and performance efficient, yielding reduction factors by three or more when compared to a truncated multiplication approach using state-of-the-art logic synthesis tools. The radix-4 squaring circuit is also shown to be more efficient than a radix-2 state-of-the-art binary squaring circuit.

We present a k-bit encoding of the k-bit binary integers based on a discrete logarithm representation. The representation supports a discrete logarithm number system (DLS) that allows integer multiplication to be reduced to addition and integer exponentiation to be reduced to multiplication. We introduce right-to-left bit serial conversion, deconversion, and unified conversion/deconversion algorithms between binary and DLS. The conversion algorithms utilize O(k) additions, do not require the use of a multiplier, and are applicable at least up to 128-bit integers. We illustrate the use of the representation in determining a novel and efficient integer power modulo 2koperation |xy|2kand compare hardware performance with a current state-of-the-art method. Furthermore, we describe properties of the conversion mappings that allow compact table lookup structures to be employed for direct conversion to and deconversion from the DLS encoding. Our lookup architecture allows 16-bit conversion and deconversion mappings to be realized with table sizes of order 2-8 Kbytes, which is up to a 64\times size reduction of the 128 Kbytes of an arbitrary 16-bits-in, 16-bits-out function table. Performance and area results that demonstrate the effectiveness of the table lookup architecture are given. The lookup methodology extends to other 16-bit integer functions such as multiplicative inverse and squaring operations.

This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.

This paper provides a review of the components of disaster tolerant computing and communications and reviews the current state in light of recent man-made terrorist events. The paper examines the relationships between disaster tolerant systems, information technology (IT) application availability and executive level management visibility necessary for successful system operations in the event of a catastrophic disaster; one which causes rapid, almost simultaneous, multiple points of failure in a system, as well as a single points of failure that escalate into wide catastrophic system failures. The technology, process and human resource challenges of traditional disaster recovery approaches to disaster preparedness are outlined. The risks of IT application downtime attributable to the increasing dependence on critical information technology applications operating in distributed and unbounded networks are explored. A general method for disaster tolerance is proposed which mitigates unplanned downtime through a disciplined approach of IT infrastructure design based on redundancy and distributed components with special attention given to the ability of executive level management to comprehend the value of uptime of an application and make appropriate capital investment. The importance of executive visibility into the system wide impact of downtime and the resultant effects on the costs of downtime of critical systems is explored.

We describe several integer function properties which in combination allow direct lookup tables to be reduced in size and structure to simpler lookup trees. Our principal result is a novel table lookup method based on a mapping of a lookup tree to a row-by-column ROM with pre and post processing logic substantially reducing the table size. Our lookup architecture allows common 16-bit integer functions such as multiplicative inverse, square, and the discrete log to be realized with table size of order 2-8 Kbytes, in comparison to the 128 Kbyte size of an arbitrary 16-bits-in 16-bits-out function table. The lookup methodology is illustrated with specific development of the 16-bit integer discrete-log function. Implementation for both unnormalized and normalized indices are synthesized into standard cell netlists and performance and area results are given that demonstrate their effectiveness.

This paper presents a decision diagram structure intended for the simulation and verification of reversible and quantum circuits. The structure is designed to efficiently represent the matrices describing reversible and quantum gate and circuit behaviour and takes advantage of key properties of those matrices. Algorithms are described for efficiently building the decision diagram representation directly from a gate without constructing the actual matrix and for performing matrix multiplication which is the fundamental operation to determine the function realized by a cascade of gates. Experimental results show the methods presented are applicable to large circuits at the state of the art in reversible and quantum synthesis and design.

We introduce a right-to-left digit serial algorithm for the integer power operation xy where x and y are positive integers. For n-bit words the algorithm utilizes o(n) additions and does not require use of a multiplier. We describe a hardware implementation and evaluate the effectiveness employing a Synopsys tool set with a standard cell implementation. Out digit serial algorithm compares favorably with a popular iterative square and multiply algorithm implemented with the same tool set.

We introduce an inheritance property and related table lookup structures applicable to simplified evaluation of the modular operations "multiplicative inverse", "discrete log", and "exponential residue" in the particular modulus 2/sup k/. Regarding applications, we describe an integer representation system of Benschop for transforming integer multiplications into additions which benefits from our table lookup function evaluation procedures. We focus herein on the multiplicative inverse modulo 2/sup k/ to exhibit simplifications in hardware implementations realized from the inheritance property. A table lookup structure given by a bit string that can be interpreted with reference to a binary tree is described and analyzed. Using observed symmetries, the lookup structure size is reduced allowing a novel direct lookup process for multiplicative inverses for all 16-bit odd integers to be obtained from a table of size less than two KBytes. The 16-bit multiplicative inverse operation is also applicable for providing a seed inverse for obtaining 32/64-bit multiplicative inverses by one/two iterations of a known quadratic refinement algorithm.

This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18/spl mu/ and 0.13/spl mu/) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13/spl mu/ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.

Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.

A technique for automatic insertion of slack matching buffers for performance enhancement in the asynchronous design style known as Phased Logic (PL) is described. A description of how slack matching buffers can offer throughput increases in PL circuitry is presented and is supported through the use of a simulation tool developed for modeling the timing behavior of PL circuits. A description of the architecture of the simulator and its implementation is also discussed. Based on the analysis of results provided by the simulator and the topological characteristics of a PL circuit, an algorithm for automatic slack matching buffer placement is devised. Examples of the buffer insertion technique are given and the effectiveness of the technique is evaluated through a set of experimental results.

Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing early evaluation functions is presented for this design style. Experimental results are given that show the increase in throughput of various benchmark circuits. The results show that as much as a 30% speedup can be achieved in some cases.

Spectral techniques have found many applications in computer-aided design, including synthesis, verification, and testing. Decision diagram representations permit spectral coefficients to be calculated via graph-based algorithms. In this paper, algorithms are described for transforming multi-output functions to produce Walsh, arithmetic, and Reed-Muller spectral decision diagrams and the experimental results of those implementations are presented.

The minimization of power consumption is an important design constraint for circuits used in portable devices. The s itching activity of a circuit node in a CMOS digital circuit directly contributes to overall power dissipation. By approximating the switching activity of circuit nodes as internal switching probabilities in Binary Decision Diagrams BDDs), it is possible to estimate the dynamic power dissipation characteristic of circuits resulting from a structural mapping of a BDD. A technique for minimizing the overall sum of switching probabilities is presented. The method is based on efficient local operations on a BDD representing the functionality of the circuit to be realized. The resulting circuit that is obtained by mapping the BDD to CMOS Pass Transistors has in simulation using a commercially available process model) shown reduced power dissipation characteristic. Experimental results on a set of MCNC benchmarks are given for this technique.

Spectral techniques are powerful methods for synthesis and verification of digital circuits. The advances in DD representations for discrete valued functions in terms of computational efficiency can be exploited in the calculation of the spectra of Boolean functions. The classical approach in computing the spectrum of a function by taking advantage of factored transformation matrices as used in the FFT may be reformulated in terms of DD based graph algorithms resulting in a complete representation of the spectrum. The relationship between DD based interpretations and the linear algebra based definitions of spectral methods are described.

A logic style known as Phased Logic (PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timed implementation. Bit level dataflow, early evaluation and automatic filtering of transient computations within PL circuits can lead to both increased performance and higher energy efficiency than the original clocked netlist. Simulation results for a 16/spl times/16 iterative multiplier based on a LUT4 design show a 23% speed improvement and 20% energy improvement over the clocked design. A Y=Y@1*a +b calculation using an array multiplier design shows a 15% performance decrease but is 2/spl times/ more energy efficient than the clocked counterpart.

The data cache organization of a computer can significantly affect overall data access latencies when a program is executed. The cache performance depends on the locality characteristics of the data being processed in a program as well as the underlying architecture. A typical executing program has a data access profile that exhibits both temporal and spatial locality characteristics. Since most processors contain single data caches at a given level and since the single data cache cannot be optimized for purely spatial nor purely temporal locality data accesses, cache space pollution and inefficient usage of cache resources can occur. In the worst case, these phenomena can actually introduce additional data access latency through repeated line fills. An analysis and modeling scheme is presented that describes the runtime data access behavior of several benchmark programs in a typical, unified data cache. The motivation for the development of this model is to produce information that may aid in the design of a split data cache with one side optimized for temporal locality accesses and the other for spatial locality accesses.

The shared binary decision diagram (SBDD) with negative edge attributes can represent many functions in a compact form if a proper variable ordering is used. In this work we describe a technique for reordering the variables in an SBDD to reduce the size of the data structure. We use a heuristic to formulate a technique for the reordering problem based on probability metrics.

A prototype system developed to convert a behavioral representation of a Boolean function in OBDD form into an initial structural representation is described and experimental results are given. The system produces a multilevel circuit using heuristic rules based on properties of a subset of spectral coefficients. Since the behavioral description is in OBDD form, efficient methods are used to quickly compute the small subset of spectral coefficients needed for the application of the heuristics. The heuristics guide subsequent decompositions of the OBDD, resulting in an iterative construction of the structural form. At each stage of the translation, the form of the decomposition is chosen in order to achieve optimization goals.

A signed binary (SE) addition circuit is presented that always produces an even parity representation of the sum word. The novelty of this design is that no extra check bits are generated or used. The redundancy inherent in a SE representation is further exploited to contain parity information.

Spectral methods for analysis and design of digital logic circuits have been proposed and developed for several years. The widespread use of these techniques has suffered due to the associated computational complexity. This paper presents a new approach for the computation of spectral coefficients with polynomial complexity. Usually, the computation of the spectral coefficients involves the evaluation of inner products of vectors of exponential length. In the new approach, it is not necessary to compute inner products, rather, each spectral coefficient is expressed in terms of a measure of correlation between two Boolean functions. This formulation coupled with compact BDD representations of the functions reduces the overall complexity. Further, some computer aided design applications are presented that can make use of the new spectrum evaluation approach. In particular, the basis for a synthesis method that allows spectral coefficients to be computed in an iterative manner is outlined. The proposed synthesis approach has the advantage that it can accommodate a wide variety of constituent gates, including XOR gates, and complex subfunctions for realizing the circuits.>