Secure computing necessitates the integration in Systems-on-Chips (SoCs) of strong Physical Unclonable Functions (PUFs) that can generate a vast amount of Challenge Response Pairs (CRPs) for cryptographic keys generation, identification and authentication. However, the excessive area cost of strong PUF designs imposes integration difficulties to SoCs of area constrained applications, such as the IoT and mobile computing. In this paper, we present a novel strong PUF design, with silicon area requirements significantly lower than those of previous strong PUFs. The proposed Current-mode Array-type Strong PUF (CAS-PUF) is based on a current source topology of only six minimum size transistors, which is tolerant to power supply variation for enhanced reliability. Compared to previous strong PUFs, the CAS-PUF achieves the same number of CRPs with 20% to 72% less area size; while for the same area size, it provides 19 to 53 orders of magnitude higher number of CRPs. Furthermore, extensive Monte Carlo simulations on CAS-PDF show a reliability of 96.45% under ±10% power supply fluctuation; and 97.69% under temperature variation (0°C to 80°C), with an average uniqueness and uniformity of 50.01% and 49.54%, respectively. Therefore, CAS-PUF can be used as a hardware root of trust mechanism to secure computing in area constrained SoCs.

SRAM-based in-memory computing (IMC) is a promising approach to overcome the bottleneck of traditional Von Neumann architectures that suffer from data transfer delay and energy inefficiency. Aging phenomena and process variations are a serious reliability and lifetime concern that may impact SRAM-based IMC array architectures, similar to conventional SRAM arrays. Bias temperature instability (BTI) is a dominant aging mechanism that degrades transistor performance and negatively affects the analog nature of the IMC computations. In this work, we present a simulation framework for the joined analysis of aging and process variation influence on IMC reliable operation. We perform, through SPICE simulations, an extensive BTI aging analysis on differential input SRAM-based IMC array architectures under different operating conditions and considering process variations. The simulation results show a substantial impact of aging on their reliability. Furthermore, we present an aging mitigation technique to maintain reliability and extend the lifetime of these circuits. Aging mitigation is achieved by periodically reconfiguring the active current paths in the IMC cells, with negligible cost on throughput and power consumption. The simulation results show that up to 68% of the IMC circuits can lose accuracy after three operating years, depending on the operating conditions. The aging mitigation technique effectively reduces the percentage of circuits that lose accuracy by up to 72% and decreases their degradation rate, essentially extending by more than$9.3\times $their reliable lifetime.

Phase change memory (PCM) is a promising non-volatile memory technology, to serve as storage class memory in modern systems. However, during write operations on PCM cells, high temperatures are locally generated for the heating of the used phase change material. The heat diffusion may influence adjacent cells (thermal crosstalk), leading to the generation of write disturb faults and the appearance of errors in the data stored in the memory array. Moreover, as technology scaling increases proximity among cells, the probability of thermal crosstalk influence is also increased. Thermal crosstalk is a key reliability challenge in PCMs. Although various techniques have been proposed to alleviate its influence, it may affect the memory operation under special conditions that maximize the heat in the neighborhood of a cell. Due to these special conditions, the corresponding write disturb faults are hard to detect. Existing testing solutions in literature are not capable of producing such conditions and may fail to cover those hard to detect faults. In this paper, we propose effective testing algorithms, capable of generating proper conditions for the activation and detection of hard to detect thermal induced write disturb faults, at a cost-efficient manner. The algorithms' complexity varies from 3MxN to 10MxN (where M and N are the number of memory array rows and columns respectively).

Secure computing necessitates hardware root of trust (RoT) integrated in Systems-on-Chips (SoCs) for cryptographic keys generation, authentication and identification. In this paper, we observe that bitflips in SRAM cells that appear while accessing multiple cells from the same bitline, are not stochastic, as previously considered, but systematic. Based on this observation, a novel strong in-memory Physical Unclonable Function (PUF) computation is proposed for harvesting static entropy from SRAM arrays. The proposed design is compatible with existing in-SRAM computing architectures. To verify our PUF operation, we implement a 6T SRAM array model that performs in-memory computing using a 32 nm CMOS Technology, and, through SPICE simulation, we evaluate the proposed PUF performance. The proposed PUF operation achieves uniqueness and uniformity of 49.99%, and 49.74%, respectively, and reliability higher than 97.4% when the temperature is varied from 0°C to 100°C, and higher than 95.2% when the nominal voltage supply is varied by 10%. Furthermore, we explore the scaling of the number of Challenge Response Pairs (CRPs) of the proposed PUF, and we compare it against the state-of-the-art. Our PUF offers orders of magnitude higher number of CRPs, therefore it is suitable for integrated mechanisms that assure secure computing in SoCs.

Digital magnitude comparators are used in digital systems to compare two binary numbers and to determine if the numbers are equal, or if one number is greater or less than the other. In this work the design of magnitude comparators in dynamic logic is examined. Two dynamic logic magnitude comparator designs are proposed and compared. One of these designs exploits an existing simplification, while the other is a totally new one. The new dynamic logic comparator design compared over the one based on the existing simplification, shows less hardware complexity, consumes less power and has lower power delay-product, for typical operand widths.

Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena degrade seriously the reliability of an SRAM. Such phenomena affect all SRAM blocks; among them the Address Decoders. Over-aged Decoders lead to potential read and/or write failures. It is imperative to develop design techniques that provide aging-tolerance in order to retain the SRAM reliable operation. An embedded circuit for the BTI and HCI aging monitoring in SRAM Decoders is presented along with an approach to react for memory repair after aging detection.

In nanometer technologies the reliability of Static Random Access Memories (SRAMs) is seriously affected by transistor Bias-Temperature Instability (BTI). In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers (due to BTI related transistor degradation) is presented. This degradation increases the input offset voltage of a sense amplifier. Periodic monitoring provides the ability to avoid SRAM failures by detecting over aged sense amplifiers (near failure) and then properly react in order to maintain the memory reliable operation. The monitoring scheme is based on a low cost differential ring oscillator, which can be easily embedded in an SRAM array without affecting the normal mode of operation.

A method and a circuitry for the periodic monitoring of the Bias-Temperature Instability (BTI) influence on SRAMs are presented in this paper. Periodic BTI monitoring provides the ability to predict failures in the memory operation, due to aging, and early react to avoid them. The proposed scheme is based on a simple, low silicon area overhead, differential ring oscillator that can be easily embedded in a typical SRAM without affecting the normal mode of operation.

Transistor aging, due to Bias-Temperature Instability (BTI) is a serious concern in Static Random Access Memories (SRAMs). Under BTI stress an SRAM cell becomes increasingly skewed, which in turn affects its performance characteristics and consequently the memory reliability. In this paper, a variation tolerant technique for the periodic monitoring of the BTI influence on SRAM cells is presented. Periodic aging monitoring provides the ability to predict oncoming failures in the memory operation and react early to avoid them. The proposed scheme is based on the duty cycle monitoring of a low cost differential ring oscillator that can be easily embedded in a typical SRAM without affecting the normal mode of operation.

Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction: leakage currents and cell state transitions. The frequently used Coupling Fault (CF) model is inadequate to model the combined effect of these mechanisms, while testing procedures using the Neighborhood Pattern Sensitive Fault (NPSF) model are not time efficient solutions. Towards this direction, we propose a new fault model, the Neighborhood Leakage and Transition Fault (NLTF) model for DRAMs, which effectively models the faulty behavior related to neighbouring cell interference. In addition, we developed a new test algorithm which is based on the NLTF model, and provides test application time reductions ranging from 68 to 87 percent with respect to the existing testing algorithms in the literature that are capable to cover the NLTFs. Finally, the proposed algorithm is extended to cover NLTFs in word-oriented DRAMs.

Timing errors are an increasing reliability concern in nanometer technology, high complexity and multi-voltage/frequency integrated circuits. A local error detection and correction technique is presented in this work that is based on a new bit flipping flip-flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip-flop. The proposed solution is characterized by very low silicon area and power requirements compared to previous design schemes in the open literature. To validate its efficiency, it has been applied in the design of a MIPS microprocessor core in a 90 nm technology, while a demonstration version of the same core in an FPGA platform is presented.

The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM cells that suffer from internal resistive opens; a weak value stored at a cell is strengthened when a sequence of read operations is applied to it. Typical DRAM testing procedures (like March tests) fail to provide enhanced coverage of resistive open defects, since they do not consider charge accumulation. This paper provides an effective test algorithm that targets resistive open defects, while considering the bit-line imbalance and the charge accumulation mechanisms.

The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double node charge sharing. Simulations results and comparisons on a variety of SEU tolerant techniques are presented to evaluate the efficiency of the proposed latch.

Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing requirements. In addition, the ability to apply this technique for at-speed scan testing is also explored in this work. According to the experimental results, the scan power consumption is drastically reduced since the signal transitions at the inputs of the combinational logic are eliminated during the scan testing operations.

Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low power scan testing operations. A low power scan version of the Razor technique is presented, which drastically reduces the scan power consumption by eliminating the signal transitions at the input of the combinational logic during the scan operations.

Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing mechanisms among these nodes, are a great concern in nanometer SRAMs, since pairs of cells are influenced. The concern is also extended to SEU related soft error tolerant latch designs, where multiple memory elements are exploited. In this work, we deal with double node charge sharing SEUs (DNCS-SEUs) that affect latch operation and we propose a new latch topology that it is capable to provide soft error tolerance under these new circumstances where single nodes or pairs of nodes are influenced by an SEU. Simulation results validate the efficiency of the new design.

Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.

Recently proposed power-gating structures for intermediate power-off modes offer significant power saving benefits as they reduce the leakage power during short periods of inactivity. Even though they are very effective for reducing static power consumption, their reliable operation can be compromised by process variations and manufacturing defects. In this paper, we propose a signature analysis technique to efficiently test power-gating structures that provide intermediate power-off modes. Based on this technique, a methodology to repair catastrophic and parametric faults, and to tolerate process variations is presented. For testing and repairing multimode power switches, we propose a robust built-in self-test and built-in self-repair scheme that reduces test cost and obviates additional manufacturing steps for post-silicon repair. Simulation results highlight the low-cost and effectiveness of the proposed method for detecting, diagnosing, and repairing defects.

As dynamic random access memories (DRAMs) are becoming denser with technology scaling, more complex fault behaviors emerge; examples are leakage, coupling effects, and cell neighborhoods interaction. The neighborhood pattern sensitive fault (NPSF) model is suitable to address such faulty behaviors and identify them during the characterization and/or test of new DRAM chips. However, NPSF test algorithms are extremely time-consuming and therefore not economically affordable. In this brief, we show how layout information can be used to refine and significantly simplify the NPSF model and reduce the test time complexity. As a case study, the folded DRAM array is considered. A realistic NPSF model, the Δ-type neighborhood, is introduced together with a time efficient test algorithm which is more than two-times cheaper than traditional ones. Even when incorporating bit-line influence and word-line coupling effects, along with NPSFs, the test algorithm time complexity almost remains unaltered. Therefore, the proposed approach makes NPSF testing economically affordable, and hence, suitable for the characterization/test of dense DRAMs in the nanoera.

Multithreshold CMOS is very effective for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme can suffer from high sensitivity to process variations, which impedes manufacturability. We propose a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. The proposed design requires less design effort and offers greater power reduction and smaller area cost than the previous method. In addition, it can be combined with existing techniques to offer further static power reduction benefits. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.

Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented, to support two of the above scenarios, which is capable to detect and locally correct timing errors. A main characteristic of the proposed flip-flop is the NBTI resistant error handling operation. Simulation results validate the efficiency of the new design.

A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting to predict rather than directly measuring a circuit's performance from its response to suitable test stimuli. In order to provide post-manufacture yield recovery through calibration, integrated RF circuits-especially nanometric circuits-are often designed to present some form of adjustability. Such a property offers a set of discrete states of operation, from which a performance-compliant state is selected by calibration. In general, an alternate test can be conducted for each discrete state of operation, thus providing a large set of test observables from which regression models can be constructed to predict performance in all available states. However, test time and cost concerns impose that the derivation of the predictive models should be performed through an optimization procedure that aims to select a subset of the test observables that minimizes a certain cost criterion. In this paper, alternate tests for adjustable RF mixers are considered where the test response consists of dc voltage levels that appear at certain circuit nodes while the mixer operates in homodyne mode. Selection algorithms are applied to determine the optimum observables from the test response. Simulations on a typical RF mixer, designed in an 0.18- μm CMOS technology, have shown significant improvement in the corresponding alternate test efficiency.

Scan testing dynamic power consumption can induce reliability problems in the circuit under test (CUT) during manufacturing testing. In this paper, we propose a scan chain partitioning technique, supported by a scan hold mechanism, for low power dissipation during the shift phase of the scan testing procedures. Substantial power reductions can be achieved either in built-in self test (BIST) or non-BIST scan-based testing environments, without test application time increase, fault coverage decrease, scan cell reordering and clock gating.

Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide timing error tolerance. The proposed and the well known Razor techniques were applied separately in the design of two versions of a 32-bit MIPS microprocessor core using a 90nm CMOS technology. Comparisons based on the experimental results validate the efficiency of the new design approach.

Power-gating structures for intermediate power-off modes offer significant power saving benefits as they reduce the leakage power during short periods of inactivity. However, reliable operation of such devices must be ensured by using adequate test methods. We propose a signature analysis technique to efficiently test power-gating structures that provide intermediate power-off modes. In particular, the proposed technique can be used to test and diagnose an efficient multi-mode power-gating architecture that was proposed recently. In addition, we propose a methodology to repair catastrophic and parametric faults, and to tolerate process variations. Analysis and extensive simulations demonstrate the effectiveness of the proposed method.

It was shown recently that signature analysis can be used for the test, diagnosis and repair of a robust multi-mode power-gating architecture. A drawback of this approach is that it requires a tester in a production-test environment, and potentially expensive manufacturing steps are necessary to repair defective power switches. We propose a built-in self-test (BIST) and built-in-self-repair (BISR) scheme for test and repair of multi-mode power switches. The proposed method reduces test cost and obviates additional manufacturing steps for post-silicon repair. In addition to eliminating the need for an external tester, it offers protection against latent defects that are manifested as errors in the field. In this way, the robust BIST/BISR solution for power switches enhances the reliability of multi-core chips that employ aggressive power management techniques. Simulation results highlight the low hardware overhead and effectiveness of the proposed method for detecting, diagnosing and repairing defects.

A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. This is a defect-oriented test scheme that dynamically sets the Mixer to operate in homodyne mode. The DC level generated at its output is used to control the oscillation frequency of a simple voltage controlled oscillator. Deviations of the oscillation frequency from the expected range of values indicate a defective Mixer. The proposed BiST technique has been applied to a typical receiver's differential RF Mixer using a 0.35μm CMOS technology. Simulation results validated the efficiency of the BiST circuit which was capable to provide a high fault coverage of catastrophic faults (which exceeds 91%) and a small test application time (1μs), at a silicon area cost approximately 16% of the Mixer area.

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated with it, compared to other fault models, restricts its wide adoption for memory testing. In this work we exploit the physical design (layout) of folded DRAM memory arrays to introduce a new neighborhood type for NPSF testing and a pertinent test and locate algorithm. This algorithm reduces drastically the test application time (about 58% with respect to the well known Type-1 neighborhood) aiming to make the NPSF model also a cost attractive choice. In addition, we introduce the Neighborhood Word-Line Sensitive Fault model and the corresponding test algorithm to cover those faults along with NPSFs, achieving test application time cost reduction from 33% to 41%, depending on various assumptions, with respect to the Type-1 neighborhood.

A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for the implementation of high fan-in embedded checkers, is presented. The new checker is characterised by high testability, high speed operation and low silicon area requirements. The circuit has been designed, for various fan-in values, in a 0.18 mum technology and electrical simulations have been carried out to validate its operation, considering process, power supply and temperature variations as well as variations of the electrical parameters.

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults

A new differential current mirror logic (DCML) family is presented. It is based on a dynamic differential topology and uses current mirrors to enhance current sensing and a sense amplifier to speed up output evaluation. Its performance in terms of delay, power and area is compared to that of cross coupled differential domino (CCDD) logic. Simulations, using a 0.18mum technology to implement high fan-in XOR/XNOR gates, were utilized to evaluate the performance of the two topologies. It is shown that for fan-ins higher than 4 the proposed logic family presents increasing reduction in delay and energy against single and multi-stage CCDD implementations, with the single-stage CCDD circuits degrading fast and being inefficient for fan-ins higher than 10. In parallel, the silicon area penalty of the DCML towards single-stage CCDD is very small and constant regardless of the gate fan-in, while multi-stage CCDDs take a much grater area than DCML which increases with the number of gates used in the multi-stage implementation

A current mode, periodic outputs, parallel two-rail code (TRC) checker, suitable for high n-variable (high fan-in) implementations, is presented. The checker is characterized by high testability, high operating frequencies and low silicon area requirements. The circuit has been designed, for various n-variable values, in a 0.18/spl mu/m technology and SPICE simulations have been carried out to validate its operation.

We propose a new concurrent soft and timing error detection circuit that exploits the time redundancy approach to achieve tolerance with respect to transient and delay faults. The idea is based on current mode sense amplifier topologies to provide fast error detection times.

Summary form only given. A new Built-in Self Test (BIST) scheme is presented that can be used for both off-line production or periodic testing of delay faults as well as for concurrent detection of faults causing signal delays in the field. The scheme is based on the I/sub DDT/ monitoring of the outputs of the circuit under test (CUT). The proposed scheme has minimal impact on the performance and silicon area of the design since the same response verifier circuit is used for both off-line and concurrent detection of errors in the field.

In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the integrated circuit (IC) can be used for path delay fault testing of the IC. We show that the testing of the IC for path delay faults can be reduced to the testing of each block. Intellectual property (IP) blocks are treated as black boxes. The number of circuit paths that must be tested is almost equal to the sum of the paths that must be tested for each block.

In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected paths to be robustly testable by 20*log/sub 2/n+2 test-vector pairs, where n is the length of the shifter. The propagation delay along all other paths is a function of the delays along the selected paths.