The simulation of spiking neural networks (SNNs) is known to be a very time-consuming task. This limits the size of SNN that can be simulated in reasonable time or forces users to overly limit the complexity of the neuron models. This is one of the driving forces behind much of the recent research on event-driven simulation strategies. Although event-driven simulation allows precise and efficient simulation of certain spiking neuron models, it is not straightforward to generalize the technique to more complex neuron models, mostly because the firing time of these neuron models is computationally expensive to evaluate. Most solutions proposed in literature concentrate on algorithms that can solve this problem efficiently. However, these solutions do not scale well when more state variables are involved in the neuron model, which is, for example, the case when multiple synaptic time constants for each neuron are used. In this letter, we show that an exact prediction of the firing time is not required in order to guarantee exact simulation results. Several techniques are presented that try to do the least possible amount of work to predict the firing times. We propose an elegant algorithm for the simulation of leaky integrate-and-fire (LIF) neurons with an arbitrary number of (unconstrained) synaptic time constants, which is able to combine these algorithmic techniques efficiently, resulting in very high simulation speed. Moreover, our algorithm is highly independent of the complexity (i.e., number of synaptic time constants) of the underlying neuron model.

Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic neural networks. This work presents an application driven digital hardware exploration where we implement realtime, isolated digit speech recognition using a Liquid State Machine (a recurrent neural network of spiking neurons where only the output layer is trained). First we test two existing hardware architectures, but they appear to be too fast and thus area consuming for this application. Then we present a scalable, serialised architecture that allows a very compact implementation of spiking neural networks that is still fast enough for real-time processing. This work shows that there is actually a large hardware design space of Spiking Neural Network hardware that can be explored. Existing architectures only spanned part of it.

Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper describes a systematic, fully automated synthesis method for integrated microsource-based optical interconnect capable of optimally sizing the interface circuits based on system specifications, CMOS technology data, and optical device characteristics. The simulation-based nature of the design method means that its results are relatively accurate, even though the generation of each data point requires only 5 min on a 1.3-GHz processor. This method has been used to extract typical performance metrics (delay, power, interconnect density) for optical interconnect of length 2.5-20 mm in three predictive technologies at 65-, 45-, and 32-nm gate length.

Supervised learning rules for spiking neural networks are currently only able to use time-to-first-spike coding and are plagued by very irregular learning curves due to their inability to model spike creation and deletion by weight changes. This paper presents a new learning rule for spiking neurons that uses the general population-temporal coding model. It is inspired by learning rules for locally recurrent analog neural networks. As a result we have a very fast learning rule that is able to operate on a wide class of decoding schemes.

We investigate the possibility to achieve band-edge lasing in optically thick gold-clad photonic-crystal (PhC) membranes, with a dielectric thickness of around 1 /spl mu/m. We have performed a two-dimensional eigenmode-expansion analysis of band-edge resonators in one-dimensional PhCs. Material thresholds, quality factors, and emission efficiencies have been calculated for TE band-edge laser resonances on the second and third /spl Gamma/-point. The second /spl Gamma/-point sustains band-edge laser modes with quality factors above 2500 for a membrane thickness of 1 /spl mu/m and a cavity length of 20 periods, however, with a very poor surface-emission efficiency. Band-edge laser modes located on the third /spl Gamma/-point have lower quality factors but higher surface-emission efficiencies. In both cases, the PhC should be designed specifically to avoid coupling with lossy, higher order modes.

This paper introduces enhancements to the SpikeProp algorithm (S. M. Bohte, et al., 2002), an error-backpropagation learning rule suited for spiking neurons using exact spike time coding. These enhancements provide additional learning rules for the synaptic delays, time constants and for the neurons' thresholds. This results in less constrained network topologies (the XOR problem for example needs up to 10 times less weights and learning convergence is up to two times faster).

Since its introduction, Donath's technique for predicting placement wire length distributions has become one of the most popular techniques for a priori wire length estimation. However, in its original form, it was heavily constrained by the underlying circuit and architecture models. In this paper, we show how a careful relaxation of those constraints results in very high correlations between predicted and experimentally measured average wire lengths as well as, a much improved accuracy in predicting wire length distributions. Because the availability of the Rent characteristic is crucial for the quality of our model, we investigate how the prediction quality degrades when only an estimated characteristic is available. Such an estimation can be required to save computation time or when the complete netlist is not yet available (partial use of typical values). It turns out that a fitted /spl beta/-model, based on only a few partitioning levels, can still result in a relatively high-prediction quality. In particular, with respect to the wire length distribution, the results are considerably better than when Rent's Rule is used.

In this paper we introduce a new algorithm for encoding analog information into spike trains, given that the reconstruction will take place using a FIR filter. An older technique called HSA is reviewed and an optimal threshold value is found. A new technique called BSA is introduced. These methods are then compared experimentally.

Over the years, different interpretations of Rent's rule and different ways of estimating the Rent parameters have emerged. In general, these parameters are extracted from the average terminal-gate relationship for a set of circuit modules. We show that this relationship (the Rent characteristic) strongly depends on the definition of the circuit modules. These can be generated in many different ways, either from the topology of the circuit graph or, in a geometric way, by cutting regions from a circuit layout. The resulting Rent parameters can be quite far apart. This paper discusses the fundamental differences between the topological and the two geometric interpretations of the Rent characteristic that are expected to be most appropriate for current wirelength estimation techniques. Our discussion is based on experimental data, as well as on a theoretical model that can be used to estimate certain geometric Rent characteristics from the topological Rent parameters. Using this model, we derive a theoretical lower limit to the value of the average geometric Rent exponent. We also study the impact of the placement approach and placement quality on the geometric Rent characteristics.

CAD applications for physical design and verification very often require enumerating all layout objects whose bounding box intersects an axis-aligned rectangular area. A number of multidimensional access methods exist to process such window queries. The performance of some important design and verification algorithms heavily depends on the processing speed of the used access method. For complex layouts, these methods require huge amounts of resident memory to attain this speed.In this paper, we present a new access method called AQUASUN, which brings a significant query processing performance improvement over other adaptive methods---methods which can cope with a continuously changing layout. These methods generally descend from the database world and are designed to perform the equivalent query in n-dimensional space. Our method is specifically tailored to two dimensions, exploiting 2D optimisations that significantly accelerate window queries within oblong objects like PCB tracks. Furthermore, AQUASUN makes use of an efficient compression technique which greatly cuts down on memory usage.

Rent's rule has been successfully applied to a priori estimation of wire length distributions. However, this approach is very restrictive: the circuits are assumed to be homogeneous. In this paper, recursive clustering is described as a more advanced model for the partitioning behavior of digital circuits. It is applied to predict the variance of the terminal count distribution. First, the impact of the block degree distribution is analyzed with a simple model. A more refined model incorporates the effect of stochastic self similarity. Finally, the model is further extended to describe the effects of heterogeneity. This model is a promising candidate for more accurate a priori estimation tools.

In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic approach for the generation and evaluation of synthetic benchmark circuits is presented. A number of existing benchmark generation methods are examined using direct validation of size and topological parameters. This exposes certain features and drawbacks of the different methods.

For the development and evaluation of computer-aided design tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.

For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits for use in evaluation tools, one could consider to actually generate such circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. However, the synthetic benchmark circuits are still very redundant, compared to existing sets of real benchmarks. It is shown that a correlation exists between the degree of redundancy and key circuit parameters.

No abstract available.

Designs targeted for FPGAs are becoming increasingly larger and more complex. The need for I/O often surpasses the number of I/O pads that can be provided at the perimeter of the FPGA chip. As a result, these designs have to be implemented in larger FPGAs, the size of which is fired by the number of I/O pads and not by the logic needed, reducing the performance of the implementation. Providing FPGA chips with I/O pads that are spread out across the whole chip area drastically reduces this problem. In this paper, we present a quantitative analysis of the impact of area-I/O in FPGAs.

A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from the start. An efficient test compaction method leads to a very compact test set, while retaining a maximum of diagnostic power and a 100% fault coverage for non-fanout circuits. An extension for fanout circuits is also presented.

Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor /spl delta//spl ap/2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

Abstract Like colour video displays and laser printers, laser photoplotters are raster scan devices. For such devices, the pixel stream representing the image must be generated in real time, and in the (scan line) order required. However, the typical size of the images photoplotters produce is an order of magnitude higher than that of video displays and laser printers, precluding the use of full‐size bitmap memories. These requirements pose particular implementation problems for the raster image processor generating the pixel stream. The parallel RIP system presented here is aimed at high‐resolution laser photoplotters, and features a largely scalable performance ranging from 40 to several hundred megapixels per second. It is built with standard components such as graphics microprocessors and VRAM memories. Its architecture is that of a distributed memory multiprocessor system with a global ring‐like topology. And most importantly, it can be programmed using the traditional sequential programming paradigm. Only minor additions are needed to sequential graphical algorithms to be executable on the system with an arbitrary number of processors. A prototype 8‐processor PRIP system has been built and tested generating printed circuit board images for a direct imaging photoplotter. The prototype exhibits a near‐linear speedup with respect to a monoprocessor solution. Architectural simulations indicate that the system can be expanded to well over 10 processors.

The authors present a high-resolution sensor composed of three ultrasonic sensors, one transmitter/receiver and two extra receivers, which allows a significant improvement in the information-extraction process. With this sensor the position (distance and bearing) of all isolated objects in an approximately 25 degrees field of view can be determined using information contained in one single snapshot of a moderately complex scene. Within limits, the sensor system can also discriminate between different types of reflectors, in particular, walls and edges, based on their radius of curvature. These results are all based on the determination of the arrival times of the echoes present at the three receivers. A noise model that accounts for the measured variations of the arrival times is used to derive limits on the resolution of the results provided by the sensor. Based on this model it is shown that, to a large extent, the sensor results are impervious to measurement variations common to all three receivers. Results obtained in a realistic environment are compared with those obtained from a conventional time-of-flight sensor.>

The authors propose a measurement setup consisting of a number of ultrasonic sensors used in parallel to perform triangulation measurements. The sensor system is based on two ideas. The first idea was to use signal processing techniques borrowed from existing radar and sonar systems. This allows the accurate determination of the position of multiple objects. Processing data in real time demands a fairly powerful processing system. The second idea was to assign a microprocessor to each transducer. To support the use of multiple sensors in the final measurement setup, transputers were used as processing elements as they offer easy scalability because of their serial links. This sensor measured the distance to multiple objects very accurately and with a resolution of 2 cm. It is shown that these techniques could be implemented in a cost-effective manner.>

It is well-known that maximum entropy distributions, subject to appropriate moment constraints, arise in physics and mathematics. In an attempt to find a physical reason for the appearance of maximum entropy distributions, the following theorem is offered. The conditional distribution ofX_{l}given the empirical observation(1/n)\sum^{n}_{i}=_{l}h(X_{i})=\alpha, whereX_{1},X_{2}, \cdotsare independent identically distributed random variables with common densitygconverges tof_{\lambda}(x)=e^{\lambda^{t}h(X)}g(x)(Suitably normalized), where\lambdais chosen to satisfy\int f_{lambda}(x)h(x)dx= \alpha. Thus the conditional distribution of a given random variableXis the (normalized) product of the maximum entropy distribution and the initial distribution. This distribution is the maximum entropy distribution whengis uniform. The proof of this and related results relies heavily on the work of Zabell and Lanford.

A stochastic model of closed-loop priority I/O systems is developed in which request generation is assumed to be exponential but service time distributions are arbitrary. This model reflects the code granularity caused by the implementation. Using this model, an interrupt-driven system is compared to a similar system with polled I/O on the basis of latency times and CPU utilization.

The peaking phenomenon of the Bayes recognition accuracy of pattern classifiers with unknown underlying statistics is addressed. It is shown that this effect, known as the Hughes paradox, arises from improper comparisons of statistically incomparable models. A formalization of the notion of comparability is introduced, and some of the results obtained in the literature are revisited in this context.

An aspect of the measurement selection problem-the existence of anomalous orderings on the probability of error obtained by selected subsets of measurements-is discussed. It is shown that for any ordering on the probability of error as a function of the subset of measurements (subject to an obvious set monotonicity condition), there exists a multivariate normal two-hypothesis problem N(μ,K) versus N(μ,K) that exhibits this ordering. Thus no known nonexhaustive sequential k-measurement selection procedure is optimal, even for jointly normal measurements.