In this work, a real-time movement decomposition-based automatic behavior analysis system is proposed. The proposed method is evaluated on a Morris water maze experiment with rat. The system integrated a high-speed tracker, a feature extraction module, and a classifier on a Xilinx Ultra-96 single computer board with a field-programmable gate array (FPGA). The high-speed tracker includes a movement predictor based on motion features and pose features, and a fast-checking algorithm to evaluate whether the tracking result is correct or not. A faster region-based convolutional neural network (Faster-RCNN)-based detector is used for initializing the tracker. The feature extraction module integrated a CNN-based feature point recognition network and a motion feature computing module. Motion and pose feature are calculated with the result of the feature points. The proposed system achieves a 66.2-frames/s processing speed, and the average point detection error is 4.01 pixels. For each video, the classification and regression tree (CART)-based classifier gives an explorative stage in five categories, which represents the rat’s strategy of exploration in Morris water maze task. This work focuses on a real-time local computing system design on small-scale datasets.

In this article, we review the existing analog resistive switching memory (RSM) devices and their hardware technologies for in-memory learning, as well as their challenges and prospects. Since the characteristics of the devices are different for in-memory learning and digital memory applications, it is important to have an in-depth understanding across different layers from devices and circuits to architectures and algorithms. First, based on a top-down view from architecture to devices for analog computing, we define the main figures of merit (FoMs) and perform a comprehensive analysis of analog RSM hardware including the basic device characteristics, hardware algorithms, and the corresponding mapping methods for device arrays, as well as the architecture and circuit design considerations for neural networks. Second, we classify the FoMs of analog RSM devices into two levels. Level 1 FoMs are essential for achieving the functionality of a system (e.g., linearity, symmetry, dynamic range, level numbers, fluctuation, variability, and yield). Level 2 FoMs are those that make a functional system more efficient and reliable (e.g., area, operational voltage, energy consumption, speed, endurance, retention, and compatibility with back-end-of-line processing). By constructing a device-to-application simulation framework, we perform an in-depth analysis of how these FoMs influence in-memory learning and give a target list of the device requirements. Lastly, we evaluate the main FoMs of most existing devices with analog characteristics and review optimization methods from programming schemes to materials and device structures. The key challenges and prospects from the device to system level for analog RSM devices are discussed.

This paper presents a novel neuroprosthetic system for perception encoding. The system consists of a wireless waterproof bi-directional neural interface and an object tracking image sensor. The neural interface features a fully programmable 8-channel neural stimulator, a compliance voltage and impedance monitoring module, a 16-channel neural recording front-end, and a duplex wireless transceiver. The image sensor features a 180×180 pixel array, with in-pixel comparator for energy efficient color thresholding based object detection tracking. A unique experiment was designed in which rats navigate a water maze using only brain stimulation to inform their location relative to a hidden platform. Custom hardware and software have been developed to support the investigation, with special attention paid to the safety of the animals during the experiment. The proposed chip designs have been fabricated in 180nm CMOS technology. This work demonstrates a novel experimental paradigm, and that the developed wireless neuroprosthetic system can be used to conduct extensive sensory encoding experiments in freely behaving animals.

This paper presents a fully integrated wireless sensor brain machine interface system to restore continuous somatosensory feedback from the hand. A wireless bi-directional neural interface system-on-chip (SoC) and a wireless sensor node design are described in this work. The neural interface integrates a 16-channel neural recording front-end, a 16-channel electrical stimulation back-end, a successive approximation analog-to-digital converter (ADC), a custom digital controller, and an ultra-wide band (UWB) wireless transceiver. The sensor node features a custom designed optical force sensor, a low-power level-crossing ADC, an UWB transmitter, and analog interface to off-chip accelerometers. The optical force sensor is developed in standard CMOS with low-cost post fabrication. Multiple sensor nodes can be used to trigger pre-defined microstimulation in different brain areas for restoring finger sensation. The prototypes have been fabricated in 180nm standard CMOS technology. Bench testing and In-Vivo experimental results are presented in this paper. The system was designed to investigate the first chronic interface to the cuneate nucleus of macaques, and showed a promising solution for sensation restoration in future neuroprosthetics.

This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing unit. A capacitor coupled instrumentation amplifier integrated input impedance boosting has been designed, dissipating 1μA quiescent current. An input referred noise of 1.63μV was measured in the frequency band of 1Hz to 7kHz. The noise efficiency factor (NEF) of the amplifier is 0.76. The SAR ADC achieves an ENOB of 10.6-bit at a sampling rate of 1MS/s. A compressed sensing processing unit with configurable compression ratio, up to 8x, was integrated in the design. The design has been fabricated in 180nm CMOS, occupying 4.5mm×1.5mm silicon area. A portable neural recorder has been built with the custom IC and a commercial low-power wireless module. A 4.6g lithium battery supports the device for a continuous compressed sensing recording up to 70 hours.

In this paper, a wireless electrogoniometer is described using a pair of ultra-wide band (UWB) wireless smart sensor nodes that are interfaced to low power 3-axis accelerometers. A high resolution SAR ADC as well as a low power asynchronous continuous sampling event-driven ADC are integrated for the digitization of the input signal under different operation modes. An anti-self-locking circuit is included in the asynchronous event-driven ADC to improve the robustness. A tri-channel UWB transceiver is designed particularly for the data transmission of the 3-axis accelerometers. A power consumption of 4.6pJ/bit is achieved for the transmitter at 10Mbps while operating under 1.2V power supply. The receiver power consumption can be as low as 0.32nJ/bit at 10Mbps under 1.8V supply. To demonstrate one application of the device, the electrogoniometer was used to quantify the in-vivo response of a somatosensory neuron to joint angle changes.

CMOS Polarization image sensors can detect the polarization of an incident light, from which a lot of information can be derived about the properties and shape of the images objects. This paper proposes a current mode polarization analyzer, based on a three-parameter polarization analysis methodology. The procedure of the calculation of the intensity, polarization degree, and the polarization angle is optimized in a format for hardware friendly implementation. The proposed analysis procedure is implemented using only absolute adder/subtractors and multiplier/dividers. In this work, the multiplier/divider is performed in two modes: i) geometric mean calculation mode, and ii) square/divider mode. Both a parallel implementation, which employs five multiplier/divider, for the optimization of processing efficiency, and a serial implementation, which employs two multiplier/divider, for the optimization of power efficiency, are designed and compared. A prototype chip of the proposed design was implemented in 0.5μm 3M2P standard CMOS technology, occupying a silicon area of 150 × 140 μm2.

In this paper, a general purpose wireless Brain-Machine-Brain Interface (BMBI) system is proposed. The system provides all the necessary hardware for a closed-loop sensorimotor neural interface. The system integrates a neural signal analyzer, two neural stimulators with different specifications, multiple body area sensory devices and a user-friendly computer interface. The neural signal analyzer features four channel analog frontend with configurable bandpass filter, gain stage, digitization resolution, and sampling rate. Digital filtering, neural feature extraction, spike detection, sensing-stimulating modulation, and compressed sensing measurement are realized in a central processing unit integrated in the analyzer. Flash memory card is activated for low power operation, compressed sensing recovery verification and/or data backup. An 8-channel stimulator with high driving capability (±10 mA with compliance voltage ±22V), and a 2-channel stimulator for deep brain stimulation are included in the proposed system. Both stimulators are capable of delivering bipolar, biphasic capacitive coupled current pulses in programmable pulse shape, amplitude, width, pulse train frequency and latency. Multi-functional wireless sensor node, including an accelerometer, a temperature sensor, and a general sensor extension port has been designed. Surveillance camera is implemented for the monitoring of the animal's behavior. A userfriendly computer interface is designed to monitor, control and configure all aforementioned devices via wireless link. Wireless closed-loop operation between the sensory devices, neural stimulators, and neural signal analyzer can be configured. Bench test and in vivo experiments are performed to verify the functions and performance of the system.

The articles in this special issue focus on applications supported by bioinspired image processing.

In this paper, a bioinspired monolithic complementary metal-oxide-semiconductor (CMOS) polarization image sensor is described as a solution to real-time polarization image capture. Metallic wire-grid gratings are integrated onto standard CMOS image sensor arrays with different orientations. A numerical analysis is performed to guide the design of the wire-grid arrays. Experimental results from different CMOS processing units are compared. A current-mode polarization processing unit is designed, fabricated, and tested in order to perform the extraction of the polarization characteristics from the captured intensities. This paper illustrates how polarization image processing can be used to monitor live cells. Several polarization processing methods with different computational complexity and data requirements have been applied and compared.

In this paper, we propose a novel low power multimode CMOS smart image sensor node with integrated focal-plane motion detection and video compression. An 80×80 image pixel array is fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm2silicon area. The proposed imager enables various operational modes, including 1) event generator mode, 2) motion tracking mode and 3) video output mode in full-resolution or compression by region of interest (ROI). An ultra low power focal-plane motion detection block, consisting of analog memory and dual-threshold comparator, is integrated in the pixel-level circuit for on-chip motion detection. A hardware-friendly motion tracking algorithm is developed that indicates ROIs according to a strategy based on the detection results. A 12-bit on-chip, off-array ADC is employed to convert the captured light intensity into digital readouts. In order to further reduce the power consumption, lower image resolution is used under the first two modes. A trade-off analysis between the image resolution and detection accuracy is proposed in this paper. In simulation, the total power consumption is 10μW at a frame rate of 30fps and a supply voltage of 3.3V in motion tracking mode. A compression ratio of 14% and an average PSNR of 42dB is achieved in compressive video output mode.

A voltage controlled MEMS oscillator (VCMO) fabricated in 65nm CMOS process is proposed in this paper. The piezoelectric aluminum nitride (AlN) Contour-Mode MEMS resonator based oscillator can be operated under multiple frequencies from 204MHz, to 517MHz, to 850MHz. A maximum overall tuning range of 611ppm is achieved at a center frequency of 204MHz. The proposed oscillator operates in the sub-threshold region, resulting in a power consumption of 47μW measured under a 0.55V power supply, which is the lowest reported in literature for an application in the 200MHz range. The measured oscillator phase noise is -77dBc/Hz at 1kHz offset from the 204MHz carrier.

A micropolarization array composed of a dual layer nano-wire polarization filters is presented. The nano-wire polarization filters are composed of 80 nm wide aluminum wires with 160 nm wire pitch. Two nano-wire polarization filters are separately patterned and etched with 6 micron square structures. The two layers are offset by 45 degrees and merged together to form the final filter. The extinction ratios of the filter are experimentally measured to be 150 and 1000 in the blue and red spectrum respectively.

A novel low power polarization image sensor is presented. This image sensor synergistically combines polymer polarization filters with a CMOS image sensor in order to compute the first three Stokes parameters at the focal plane. The carefully optimized microfabrication procedure for the pixel-pitch polymer polarization filters is described in detail in this paper. The imaging array is composed of 60 by 20 pixels and consumes 15mW at 30fps. A demo of the completed polarization image sensor will be given to illustrate how objects of similar luminescence can be discriminated based on their polarimetric properties.

A complete polarization image sensor composed of a 60 by 20 pixel array with on-chip analog processing and an integrated pixel-pitch polymer polarization filter is presented. The image sensor computes the first three Stokes parameters at the focal plane at 30 fps with 15 mW power consumption. The sensor is used to identify automatically material properties by computing the degree of polarization off chip.

A novel 1.5 transistors per pixel linear current mode active pixel sensor (APS) is presented. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the read-out and reset transistor. The column FPN of 0.4% and SNR of 43dB is measured. The total power consumption is 5mW at 30fps. A theoretical framework for optimizing temporal and spatial noise is presented.

This paper describes a current-mode active pixel sensor (APS) for low supply voltage, low noise and high resolution/high speed imaging applications. The imager is designed in a standard 0.25μm 2.5V CMOS process. A transistor count of 1.5 per pixel is achieved through transistor sharing and floating diffusion (FD) based addressing. Highly linear current readout in velocity saturation, as well as triple sampling (TS), are used to reduce fixed pattern noise (FPN). Dynamic range (DR) is improved through FD presetting and boosting techniques, which allow the full-well capacity of photodiodes to be utilized without degrading readout linearity. Post-extraction simulation results on FPN and DR are presented, and compared favorably to a conventional 3-transistor pixel design.

This paper describes a switched-current successive approximation ADC for high resolution current mode imagers. The ADC is suitable to be integrated at the column level and operate in parallel. Designed in a 0.25µm CMOS process, its core occupies only 24μm×200μm and consumes 930μW. Having a low input impedance of 0.6Ω, it can connect directly to the imaging array while providing a stable bias voltage on the input line. The ADC is built around a single current comparator and an 11-bit sub-binary current DAC. It has no sampling stages. The output is digitally calibrated in order to compensate for component mismatch. Simulation results on both static and dynamic performance are presented. With calibration, the ADC achieves an effective resolution of 10 bits at 8.3MS/s.

A novel current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is 0.35% of the saturated current. A discussion on theoretical temporal noise limitations of this design is also presented.

This paper described a novel current-mode active pixel sensor (APS) imager. Conversion of photodiode voltage to output current is done using transistors operating in velocity saturation region. The high output impedance of this region makes it more suitable for current-sourcing operation than the linear region. The transistors also exhibit high linearity, allowing us to suppress fixed pattern noise (FPN) by correcting for both offset and gain variations among pixels. Experimental results on the fabricated 110times200 pixel array are presented. With conventional correlated double sampling (CDS), FPN is reduced from 3.8% to 0.85%. Further reduction requires compensation of gain variations, and results in a final FPN of 0.19%. A triple sampling approach is introduced to implement the described correction in hardware.

Complex spatio-temporal patterns can be clustered using a network of parametrically coupled logistic maps. This paper describes the processing element design of such a Cort-X system. Each Cort-X element consists of a non-linear coupling (LC) and a non-linear dynamic element (IRON). The circuits are designed for low-power operation and to be robust against process variations. This has been accomplished by using open-loop circuits, and a self-calibration technique that compensate for process variations. The circuits were implemented in a 0.25 mum, 2.5V CMOS process and consumes a total of 12mW of power at 1MHz which is about a factor of 20 less power than previous realizations. This opens the possibility for building a large-scale Cort-X system on a chip for the recognition of complex spatio-temporal patterns.

In this paper, a novel method for single-channel speech enhancement is proposed, which is based on a spectral conversion feature denoising approach. Spectral conversion has been applied previously in the context of voice conversion, and has been shown to successfully transform spectral features with particular statistical properties into spectral features that best fit (with the constraint of a piecewise linear transformation) different target statistics. This spectral transformation is applied as an initialization step to two well-known single channel enhancement methods, namely the iterative Wiener filter (IWF) and a particular iterative implementation of the Kalman filter. In both cases, spectral conversion is shown here to provide a significant improvement as opposed to initializations using the spectral features directly from the noisy speech. In essence, the proposed approach allows for applying these two algorithms in a user-centric manner, when “clean” speech training data are available from a particular speaker. The extra step of spectral conversion is shown to offer significant advantages regarding output signal-to-noise ratio (SNR) improvement over the conventional initializations, which can reach 2 dB for the IWF and 6 dB for the Kalman filtering algorithm, for low input SNRs and for white and colored noise, respectively.

A novel focal plane imaging sensor capable of real time extraction of polarization information is presented. The imaging system consists of a photo array of 256 by 256 linear current mode active pixel sensors (APS). Analog processing circuitry is included at the focal plane for noise suppression and computation of the Stokes parameters. The imaging sensor was fabricated in 0.18mum process with 10mum pixel pitch and 75% fill factor. An array of micro polarizer is designed and fabricated separately and is mounted on top of the imaging array. Simulation results of the imaging sensor are presented

An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image.

A thin film polarizer has been patterned and etched using reactive ion etching (RIE) in order to create 14 micron circular periodic structures. The polarization thin film has extinction ratio of 60dB in the blue and green visible spectrum and /spl sim/40db in the red spectrum. Various gas combinations for RIE has been explored and it has been experimentally determined that for a particular concentration of CF/sub 4/ and O/sub 2/ an optimum etching rate, in terms of speed and under-etching, is possible. Theoretical explanation for the optimum etching rate has been also presented. In addition, anisotropic etching with less then 0.5/spl mu/m under cutting has been achieved. Experimental results of the patterned structures under polarized light are presented.

We present a CMOS image sensor capable of both voltage- and current-mode operations. Each pixel on the imager has a single transistor acting as either source follower for voltage readout, or transconductor for current readout. The two modes share the same readout lines, but have their own correlated double sampling (CDS) units for noise suppression. We also propose a novel current-mode readout technique using a velocity-saturated short-channel transistor, which achieves high linearity. The 300/spl times/200 image array is a mixture of 3 types of pixels with identical photodiodes and access switches; while the readout transistors are sized for their designated mode of operation. This ensures a fair comparison on the performance of the different modes.

In a macroscopic approach, a single-chip cortical patch is designed based on the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabricated in a 0.6 mum CMOS process, and is driven under signals with 1 MHz frequency. It covers a die has an area of 0.2 mm2, and consumes 40 mW power, with a 5 V supply

A nonlinear interconnection module for a corticonic network is designed and fabricated in a 0.6 mum CMOS process. The module uses NMOS transistors in weak-inversion region for nonlinearity. A calibration scheme is developed to compensate for the process and temperature variation of the circuit. The designed module has an area of 0.35mm2. It consumes 200mW of power, with 5V power supply. Simulation results show that the circuit is able to implement the target parametric coupling function accurately

The objective of voice conversion algorithms is to modify the speech by a particular source speaker so that it sounds as if spoken by a different target speaker. Current conversion algorithms employ a training procedure, during which the same utterances spoken by both the source and target speakers are needed for deriving the desired conversion parameters. Such a (parallel) corpus, is often difficult or impossible to collect. Here, we propose an algorithm that relaxes this constraint, i.e., the training corpus does not necessarily contain the same utterances from both speakers. The proposed algorithm is based on speaker adaptation techniques, adapting the conversion parameters derived for a particular pair of speakers to a different pair, for which only a nonparallel corpus is available. We show that adaptation reduces the error obtained when simply applying the conversion parameters of one pair of speakers to another by a factor that can reach 30%. A speaker identification measure is also employed that more insightfully portrays the importance of adaptation, while listening tests confirm the success of our method. Both the objective and subjective tests employed, demonstrate that the proposed algorithm achieves comparable results with the ideal case when a parallel corpus is available.

In this paper we demonstrate that spectral conversion can be successfully applied to the speech enhancement problem as a feature denoising method. The enhanced spectral features can be used in the context of the Kalman filter for estimating the clean speech signal. In essence, instead of estimating the clean speech features and the clean speech signal using the iterative Kalman filter, we show that is more efficient to initially estimate the clean speech features from the noisy speech features using spectral conversion (using a training speech corpus) and then apply the standard Kalman filter. Our results show an average improvement compared to the iterative Kalman filter that can reach 6 dB in the average segmental output Signal-to-Noise Ratio (SNR), in low input SNR's.

The objective of voice conversion methods is to modify the speech characteristics of a particular speaker in such manner, as to sound like speech by a different target speaker. Current voice conversion algorithms are based on deriving a conversion function by estimating its parameters through a corpus that contains the same utterances spoken by both speakers. Such a corpus, usually referred to as a parallel corpus, has the disadvantage that many times it is difficult or even impossible to collect. Here, we propose a voice conversion method that does not require a parallel corpus for training, i.e. the spoken utterances by the two speakers need not be the same, by employing speaker adaptation techniques to adapt to a particular pair of source and target speakers, the derived conversion parameters from a different pair of speakers. We show that adaptation reduces the error obtained when simply applying the conversion parameters of one pair of speakers to another by a factor that can reach 30% in many cases, and with performance comparable with the ideal case when a parallel corpus is available.

The iterative Wiener filter (IWF) for speech enhancement in additive noise is an effective and simple algorithm to implement. One of its main disadvantages is the lack of proper criteria for convergence, which has been shown to introduce severe degradation to the estimated clean signal. Here, an improvement of the IWF algorithm is proposed, when additional information is available for the signal to be enhanced. If a small amount of clean speech data is available, spectral conversion techniques can be applied for estimating the clean short-term spectral envelope of the speech signal from the noisy signal, with significant noise reduction. Our results show an average improvement compared to the original IWF that can reach 2 dB in the segmental output signal-to-noise ratio (SNR), in low input SNRs, which is perceptually significant.

A new auditory-based speech processing system based on the biologically rooted property of the average localized synchrony detection (ALSD) is proposed. The system detects periodicity in the speech signal at Bark-scaled frequencies while reducing the response's spurious peaks and sensitivity to implementation mismatches, and hence presents a consistent and robust representation of the formants. The system is evaluated for its formant extraction ability while reducing spurious peaks. It is compared with other auditory-based and traditional systems in the tasks of vowel and consonant recognition on clean speech from the TIMIT database and in the presence of noise. The results illustrate the advantage of the ALSD system in extracting the formants and reducing the spurious peaks. They also indicate the superiority of the synchrony measures over the mean-rate in the presence of noise.

In this work, a feature-based system for the automatic classification of stop consonants, in speaker independent continuous speech, is reported. The system uses a new auditory based speech processing front-end that is based on the biologically rooted property of average localized synchrony detection (ALSD). It incorporates new algorithms for the extraction and manipulation of the acoustic-phonetic features that proved, statistically, to be rich in their information content. The experiments are performed on stop consonants extracted from the TIMIT database with additive white Gaussian noise at various signal-to-noise ratios. The obtained classification accuracy compares favorably with previous work. The results also showed a consistent improvement of 3% in the place detection over the generalized synchrony detector (GSD) system under identical circumstances on clean and noisy speech. This illustrates the superior ability of the ALSD to suppress the spurious peaks and produce a consistent and robust formant (peak) representation.

In this paper, the acoustic-phonetic characteristics of the American English stop consonants are investigated. Features studied in the literature are evaluated for their information content and new features are proposed. A statistically guided, knowledge-based, acoustic-phonetic system for the automatic classification of stops, in speaker independent continuous speech, is proposed. The system uses a new auditory-based front-end processing and incorporates new algorithms for the extraction and manipulation of the acoustic-phonetic features that proved to be rich in their information content. Recognition experiments are performed using hard decision algorithms on stops extracted from the TIMIT database continuous speech of 60 speakers (not used in the design process) from seven different dialects of American English. An accuracy of 96% is obtained for voicing detection, 90% for place of articulation detection and 86% for the overall classification of stops.

In this paper, a new auditory-based speech processing system based on the biologically rooted property of average localized synchrony detection (ALSD) is proposed. The system detects periodicity in the speech signal at Bark-scaled frequencies while reducing the response's spurious peaks and sensitivity to implementation mismatches, and hence presents a consistent and robust representation of the formants. The system is evaluated for its formant extraction ability while reducing spurious peaks. It is compared with other auditory-based front-end processing systems in the task of vowel recognition on clean speech from the TIMIT database and in the presence of noise. The results illustrate the advantage of the ALSD system in extracting the formants and reducing the spurious peaks. They also indicate the superiority of the synchrony measures over the mean-rate in the presence of noise.

The acoustic-phonetic characteristics and the automatic recognition of the American English fricatives are investigated. The acoustic features that exist in the literature are evaluated and new features are proposed. To test the value of the extracted features, a knowledge-based acoustic-phonetic system for the automatic recognition of fricatives, in speaker independent continuous speech, is proposed. The system uses an auditory-based front-end processing and incorporates new algorithms for the extraction and manipulation of the acoustic-phonetic features that proved to be rich in their information content. Several features, which describe the relative amplitude, location of the most dominant peak, spectral shape and duration of unvoiced portion, are combined in the recognition process. A recognition accuracy of 95% for voicing detection and 93% for place of articulation detection are obtained for TIMIT database continuous speech of 22 speakers from 5 different dialect regions.

The use of complex noise transfer functions for bandpass sigma delta modulation is described and compared with real transfer functions. For bandpass signals centered at higher frequencies, the use of complex noise transfer functions (NTFs) allows performance improvements over a modulator of the same order using real transfer functions. Results are presented that show the performance improvement possible using complex second order modulators.

The majority of neural network based speech recognition models currently employed are simulated on digital computers. While appropriate for the laboratory environment, low cost digital computers do not have the computational power required to simulate neural network recognition systems in real time. Speech recognition models based on neural networks can be realized in analog hardware where circuits can be made that operate in real-time. This paper presents results from an on-going project to implement a speech recognition system on a general purpose analog neurocomputer. In particular, the input stages of the recognition system are presented. These stages consist of analog band-pass filters and feature detectors for energy onset, offset, motion, pause, and duration.

A multi band approach to oversampled noise shaping analog to digital conversion is described. The multi band A/D converter breaks the signal band into several smaller bands and uses a different band reject noise shaping transfer function for each band. A FIR filter bank attenuates the out-of-band noise for each band and reconstructs the signal. This approach allows performance improvements over conventional noise shaping A/D converters which convert the entire signal band using one noise shaping transfer function. A design example and simulation results where a signal with 512 kHz bandwidth is converted to about 16 bits of resolution is presented.>

A prototype programmable analog neural computer and selected applications are described. The machine is assembled from over 100 custom VLSI modules containing neurons, synapses, routing switches and programmable synaptic time constants. Connection symmetry and modular construction allow expansion to arbitrary size. The network runs in real time analog mode, however connection architecture as well as neuron and synapse parameters are controlled by a digital host that monitors also the network performance through an A/D interface. Programming and monitoring software has been developed and several application examples including the dynamic decomposition of acoustical patterns are described. The machine is intended for real time, real world computations including ATR. In current configuration its maximal speed is equivalent to that of a digital machine capable of more than 1011 flops. A much larger machine is currently under development.