A Freeze Vernier delay line time-to-digital converter for very low power and high resolution is presented. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the start line can be frozen by the stop line, omitting the power-hungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with additional circuitry. The TDC core consists of inverters and current-enabled inverters only. A proof-of-concept design has been implemented in 65nm CMOS with a typical resolution of 4.88ps, a dynamic energy consumption of 106.22fJ per conversion and a combined gate width of 96μm.

To improve the accuracy of static timing analysis, the traditional nonlinear delay models are increasingly replaced by more physical gate models, such as current source models and transistor-level gate models. However, the extension of these accurate gate models for statistical timing analysis is still challenging. In this paper, we propose a novel statistical timing analysis method based on transistor-level gate models. The accuracy and efficiency are obtained by using an efficient random differential equation based solver. The correlations among signals and between input signals and delay are fully accounted for. In contrast to Monte Carlo simulation solutions, the variational waveforms for statistical delay calculation are obtained by simulating only once. At the end of statistical timing analysis, both the statistical delay moments and the variational waveforms are available. The proposed algorithm is verified with standard cells and ISCAS85 benchmark circuits in a 45-nm technology. The experimental results indicate that the proposed method can capture multiple input simultaneous switching for statistical delay calculation, and can provide 0.5% error for delay mean and 2.7% error for delay standard deviation estimation on average. The proposed statistical simulation introduces a small runtime overhead with respect to static timing analysis runtime. The MATLAB implementation of the proposed algorithm has two orders of magnitude speedup, compared to Spectre Monte Carlo simulation.

The impact of crosstalk effects on timing performance is increasing as the device geometries are shrinking. As a consequence, crosstalk effects need to be considered in statistical timing analysis for higher accuracy. In this letter, the statistical interconnect delay due to crosstalk effects is calculated based on a piecewise linear delay change curve model (PLDM), which enables fast closed-form analytical delay evaluation. The PLDM-based method is independent of the delay change characteristics and is able to handle both Gaussian and non-Gaussian input skew distributions. The proposed method can be integrated into a statistical timing analyzer with runtime proportional to the number of samples for PLDM characterization. Experimental results demonstrate that the proposed method can estimate the delay mean and standard deviation for coupled RC interconnects at PTM 65-nm technology with errors better than${-}{0.07\%}$and${-}{1.23\%}$, respectively, with only 20 samples for PLDM characterization. In addition, the proposed method typically achieves two to three orders of magnitude speedup compared to Monte Carlo simulations.

In 3-D integrated circuits, accurate runtime sensing of on-chip temperature is required to establish dynamic thermal management instruction sets. Placement restrictions and excessive runtime thermal variations, however, compromise the performance and reliability of the sensor readings. Within this framework, a novel methodology for thermal estimation based on unscented Kalman filter, augmented only with a limited number of temperature sensors at a few selected locations, is proposed. In addition, we extend discontinuous Galerkin finite-element method to include coupling mechanism between neighboring grid cells for accurate thermal profile estimation and introduce a balanced stochastic truncation to find a low-dimensional but accurate approximation of the thermal network over the whole frequency domain. As the experimental results show, the runtime thermal estimation method reduces temperature estimation errors by an order of magnitude.

As the device geometries are shrinking, the impact of crosstalk effects increases, which results in a stronger dependence of interconnect delay on the input arrival time difference between victim and aggressor inputs (input skew). The increasing process variations lead to statistical input skew which induces significant interconnect delay variations. Therefore, it is necessary to take input skew variation into account for interconnect delay calculation in the presence of process variations. Existing timing analysis tools evaluate gate and interconnect delays separately. In this paper, we focus on statistical interconnect delay calculation considering crosstalk effects. A piecewise linear delay-change-curve model enables closed-form analytical evaluation of the statistical interconnect delay caused by input skew (SK) variations. This method can handle arbitrarily distributed SK variations. The process-variation (PV)-induced interconnect delay variation is handled in a quadratic delay model which considers coupling effects. The SK- and PV-induced interconnect delay variations are combined together for crosstalk-aware statistical interconnect delay calculation. The experimental results indicate that the proposed method can predict the interconnect delay impacted by both input skew variation and process variations with average (maximum) absolute mean error 0.25% (0.75%) and standard deviation error 1.31% (3.53%) for different types of coupled wires in a 65nm technology.

To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propose a novel correlation-preserving statistical timing analysis method based on transistor-level gate models. The correlations among signals and between process variations are fully accounted for. The accuracy and efficiency are obtained from statistical transistor-level gate models, evaluated using a smart Random Differential Equation (RDE)-based solver. The variational waveforms are available, allowing signal integrity checks and circuit optimization. The proposed algorithm is verified with standard cells, simple digital circuits and ISCAS benchmark circuits in a 45 nm technology. The results demonstrate the high accuracy and speed of our algorithm.

This paper reports design, efficiency and measurement results of the temperature sensor based on substrate bipolar transistors and a PTAT multiplier for adaptive thermal monitoring of deep-submicron VLSI circuits. The prototype temperature sensor with un-calibrated 3σ accuracy of 0.9°C within a 0°C-160°C temperature range has been fabricated in standard single poly, six metal 90nm CMOS, consumes only 11μW at 1V power supply and measures 0.05mm2.

This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design.

This paper proposes a highly efficient methodology for the statistical analysis of RC nets subject to manufacturing variabilities, based on the combination of parameterized RC extraction and structure-preserving parameterized model order reduction methods. The sensitivity-based layout-to-circuit extraction generates first-order Taylor series approximations of resistances and capacitances with respect to multiple geometric parameter variations. This formulation becomes the input of the parameterized model order reduction, which exploits the explicit parameter dependence to produce a linear combination of multiple non-parameterized transfer functions weighted by the parameter variations. Such a formulation enables a fast computation of statistical properties such as the standard deviation of the transfer function given the process spreads of the technology. Both the extraction and the reduction techniques avoid any parameter sampling. Therefore, the proposed method achieves a significant speed up compared to the Monte Carlo approaches.

This paper introduces a novel compact implicit model for a probabilistic set of waveforms (PSoW) which arise as representations for uncertain signal waveforms in Statistical Static Timing Analysis (SSTA). In traditional SSTA tools, signals are just represented as (distributions of) arrival time and slew. In our approach, to increase accuracy, PSoW's are used instead. However, to represent PSoW's explicitly, a very large amount of data is necessary, which can be problematic. To solve this problem, a compact implicit model is introduced, which can be characterized with just a handful of parameters. The results obtained show that the implicit model can generate real-life PSoW's with high accuracy.

Existing industry-practice statistical static timing analysis (SSTA) engines use black-box gate-level models for standard cells, which have accuracy problems as well as require massive amounts of CPU time in Monte-Carlo (MC) simulation. In this paper we present a new transistor-level non-Monte Carlo statistical analysis method based on solving random differential equations (RDE) computed from modified nodal analysis (MNA). In order to maintain both high accuracy and efficiency, we introduce a simplified statistical transistor model for 45nm technology and below. The model is combined with our new simulation-like engine which can do both implicit non-MC statistical simulation and deterministic simulation fast and accurately. The statistics of delay and slew are calculated by means of the proposed analysis method. Experiments show the proposed method is both run time efficient and very accurate.

In this paper, we will develop an analytic approach to estimate the statistical properties (mean and variance) of the performance of a uniformly buffered global IC interconnect, based on the mean and (co)variance of the appropriate design and technology parameters. Compared to other approaches, such as Monte Carlo based approaches, our analytic approach would allow a much tighter design optimization loop and provide a better insight in the factors involved. The model that we use is generic, but in this paper we assume a set of synthetic (not based on actual process data) but realistically large values for the variability of the input parameters. Under these assumptions, it follows that solutions for the area/power/performance tradeoff that are optimal in a deterministic setting, might suffer from excessive variability, potentially leading to a yield problem.

For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling ef-fects. Basically, either a Finite Element Method (FEM) or a Boundary Element Method (BEM) can be used. The FEM is the most versatile and flexible whereas the BEM is faster, but requires a stratified, layout-independent doping profile for the substrate. Thus, the BEM is unable to properly model any specific, layout-dependent doping patterns that are usually present in the top layers of the substrate, such as channel stop layers. This paper describes a way to in-corporate these doping patterns into our substrate model by combining a BEM for the stratified doping profiles with a 2D FEM for the top-level, layout-dependent doping pat-terns, thereby achieving improved flexibility compared to BEM and improved speed compared to FEM. The method has been implemented in the SPACE layout to circuit ex-tractor and it has been successfully verified with two other tools.

In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately modeling the properties of the substrate as a noise-propagator is becoming ever more important. A model can be obtained through the Finite Element Method (FEM) or the Boundary Element Method (BEM). The FEM performs a full 3D discretization of the substrate, which makes this method very accurate and flexible but also slow. The BEM only discretizes the contact areas on the boundary of the substrate, which makes it less flexible, but significantly faster. A combination between BEM and FEM can be efficient when we need flexibility and speed at the same time. This paper briefly describes the BEM and the FEM and their combination, but mainly concentrates on the theoretical validation of the combined method and the experimental verification through implementation in the SPACE layout to circuit extractor and comparison with commercial BEM and FEM tools.

We extend the partial inductance concept by replacing the magnetic interaction between open filaments i and j by that between filament j and a (finite) closed loop, formed by connecting the endpoints of a filament pair (i-i/sup l/). The secondary filament i/sup l/ is constructed by radial projection of filament i onto a cylindrical shell around filament j. We show that, although individual partial inductance values are modified, the inductive behaviour of the full circuit is invariant. Mutual inductances of distant filaments are particularly reduced, because the far field of a conductor loop falls off much faster than that of a single filament. Therefore, it is expected that subsequent removal of such transformed off-diagonal elements from the partial inductance matrix has less effect on the overall inductive properties, so our method provides a tool to enhance robustness under matrix sparsification. We call our method "virtual screening", because the screening filaments (i/sup l/) are not physically present. Symmetry of the inductance matrix is presented for orthogonal networks only. We also present an extension of our method to a more general class of shells. This allows a detailed comparison of the virtual screening method and the "potential shift-truncate method", introduced with spherical equipotential shells (B. Krauter and L.T. Pileggi, 1995) and extended to ellipsoidal equipotential shells (M. Beattie et al., 1998). We find strong similarities, but also differences. An interesting result is the fact that the virtual screening method with tubular shells applied to orthogonal networks can be interpreted as a generalization of the potential shift-truncate method to non-equipotential shells, which also implies that preservation of stability is guaranteed.

This paper presents a technique that transforms large and complex RC networks into much smaller, physically realizable RC networks. These models reflect the transmission behavior of the initial network accurately for frequencies up to a user-defined maximal signal frequency. This technique has been incorporated in a layout-to-circuit extractor, using a scan-line approach. The method guarantees numerical stability and performs excellently in modeling RC interconnects. 1 Introduction This paper presents a solution to the major problem how to obtain a simple, passive and physically realizable RC network that matches the transmission behavior of a given very large and complex RC network up to a predefined maximal signal frequency. This problem is particularly acute in (3-D) layout-to-circuitextraction, where appropriate models for the IC interconnections in VLSI designs have to be generated. In most VLSI circuits, the IC interconnections and their parasitics play an essential role in th...

In this paper, we describe how we have improved the efficiency of a finite-element method for interconnect resistance extraction by introducing articulation nodes in the finiteelement mesh.The articulation nodes are found by detecting equipotential regions and lines in the interconnects.Without generating inaccuracies, these articulation nodes split the finite-element mesh into small pieces that can be solved independently.The method has been implemented in the layoutto-circuit extractor Space.All interconnect resistances of a circuit containing 63,000 transistors are extracted on an HP 9000/735 workstation in approximately 70 minutes.

In this paper we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to increasing operating frequencies, microwave-like effects will become important. Therefore stronger demands are put on extraction and verification tools. We indicate the state-of-the-art for capacitance, resistance and substrate resistance extraction and discuss some open problems. We also discuss several model reduction techniques as well as issues related to simulation and implementation in a CAD system.

To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory. 1 Introduction The values of the interconnect resistances in modern integrated circuits tend to increase. This is caused by the fact that, due to down-scaling, the widths of the wires are decreased. Also, due to the increase in chip size, the average length of the wires increases. Significant values for interconnect resistances in integrated circuits may cause malfunctioning of the circuit, e.g. because of too large delay time values or because of too great ...

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. The paper proposes a boundary element method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification. In contrast to standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by various simulation packages, such as Spice. The efficiency and accuracy of the extractor are confirmed by experimental results and enable a fast and reliable layout verification for both MOS and bipolar/BiCMOS technologies.

For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchical capacitance extraction method that efficiently extracts 3D interconnect capacitances of large regular layout structures such as RAMs and array multipliers. The method is based on a 3D capacitance extraction method that uses a boundary-element technique and approximate matrix inversion to efficiently compute 3D interconnect capacitances for flat layout descriptions. The latter method has a computational complexity O(Z), where Z is the size of the layout. In the worst case, the hierarchical extraction method has computational complexity O(B+U), where B is the total size of the boundary area between all circuit parts in which the circuit is decomposed, and U is the total size of the parts of the circuit that are unique. The method has been implemented in the layout-to-circuit extractor SPACE that uses as input a hierarchical layout description of the circuit. It produces as output a netlist containing transistors, resistances, ground capacitances, and coupling capacitances between conductor parts that are near to each other.

We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits.The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors.This yields a system of Green's function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other.With N representing the size of the layout this results in time and space complexities of O(N) and O{&) respectively.The method has been implemented in an efficient layout to circuit extractor and experimental results are presented.