The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS), implemented in an FPGA, is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm that does not distort the magnitude of the sine and cosine outputs. This algorithm maps well into the DSP slices present in modern FPGAs. Implemented in a Xilinx Virtex-7 device, the design dissipates 54.9 mW of power at 1 GHz, a performance previously attainable only in ASIC designs.

A new digital modulator has a very efficient implementation. A 0.18-μm CMOS prototype, fabricated at TSMC, runs at clock-rates up to 275 MHz and dissipates less than 40 mW. At the 250 MHz design target, it dissipates 34.2 mW.

Recursive polyphase cascaded integrator-comb (CIC) prefilters are proposed to greatly increase the speed of digital decimation so as to address demands of high speed sigma-delta ADCs that over-sample at several GHz. The recursive computations in the new method avoid the substantial area/complexity increases in traditional polyphase decomposition implementations. Clock rate improvements by factors of 2 or 4 can be achieved, in comparison to those of traditional CIC filters. Implemented in a 0.18-μm CMOS process, a decimate-by-16 prefilter achieves a 1.2 Gb/s clock rate in the slow corner after post-route extraction, while occupying 0.08 mm2area.

The architecture of a frequency synthesizer that generates an arbitrary-frequency output clock from an arbitrary-frequency input clock is presented. This design supports fully-programmable synthesis ratios, including integer-N, fractional-N and rational-K/L ratios. An earlier solution presented by the authors requires an input clock frequency above a few hundred mega-hertz for a low phase noise output clock. In the present work, a digital noise-canceling technique is introduced to eliminate the noise contribution from the input frequency divider, thus allowing an input clock rate reduction down to tens of mega-hertz.

A programmable rational-K/L frequency multiplier that can synthesize any frequency between 25 MHz and 6 GHz from an input clock ranging from 1 GHz to 5.5 GHz is presented. The architecture employs a fractional-N input clock divider followed by a fractional-N PLL. In contrast to conventional architectures, it allows large K and L, whose maximum values are only limited by the word-length of digital ∑Δ modulators. Additionally, to accommodate large Kvcovariation, which is inevitable in wide tuning range VCOs, Kvcocompensation is implemented without involving additional circuitry. This is an ideal solution to support a programmable serializer/deserializer on an FPGA.

Rovini, et al., have proposed a delta-based layered decoding algorithm to mitigate the latency constraint imposed by the layered decoding algorithm on QC-LDPC codes whose adjacent block rows overlap. We apply their algorithm and the low-complexity offset-based Min-Sum check equation to the decoding of the codes specified in WiMAX. The performance is simulated for two representative hardware pipeline depths, showing a maximal 0.13-dB performance loss, with respect to the ideal latency-free layered decoding algorithm, for a block error rate of 10−2in 15 iterations and a pipeline depth of eight. We further develop a systematic procedure to arrange the processing order of the block rows and block columns of a given QC parity check matrix, reducing the aforementioned performance loss to 0.03 dB at no extra hardware cost. The procedure can be applied to any QC-LDPC codes for any given pipeline depths.

A method for designing square-root (SR) FIR filters that are less sensitive to receiver clock jitter is proposed. Unlike previously published methods that use only frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. Design examples show that using the time-domain constraints can result in a more robust eye opening and thus a robust ISI performance in the presence of receiver clock jitter.

A high-speed turbo FEC code was proposed in the HomePlug AV standard for 200-Mbps high-data-rate home networking systems over power lines. In this paper, we demonstrate an efficient implementation of the FEC core to meet the high throughput requirement with lowered latency and lowered memory costs. The performance enhancement is achieved by combining radix-16 encoding with a time-shared conflict-avoidance memory access structure in the encoder, and by employing an optimized sub-bank parallel decoding architecture in the iterative decoder. A low-latency design can reduce the TX/RX turn-around time and the minimum inter-frame spacing required in a shared network, hence improving overall network utilization

In this paper, a systematic method for designing linear-phase (LP) square-root (SR) FIR filters is proposed. The proposed method employs a constrained optimization algorithm to design the coefficients of the desired FIR filter. Unlike the previously published method that used the Remez exchange algorithm, the proposed method relaxes the passband equiripple constraint imposed by the Remez exchange algorithm. Design examples show that relaxing the passband constraint can result in better stopband attenuation and inter-symbol interference performance or a shorter SR filter.

A reconfigurable Viterbi decoder capable of accommodatingKfrom 6 to 9, andr= 1/2 and 1/3 has been implemented on a programmable multiprocessor, fabricated in TSMC 0.18-μm CMOS. Efficient trellis partitioning and path metric memory localization techniques endow the Viterbi decoder with simple configuration control and high efficiency. For this Viterbi decoder, performance can be traded off in favor of power savings, or vice-versa.

An energy circulation technique is shown to unite an even number of oscillation tanks to form an integrated oscillator. It reduces phase noise and boosts the figure-of-merit beyond that which is achievable by a differential VCO while generating quadrature phase. The measured phase noise of a two-way configuration at 1 MHz offset is -132.6 dBc/Hz while drawing 27.7 mW from a 1.8 V supply. In simulation, the four-way configuration further reduces the phase noise by 3 dBc/Hz. Techniques for correcting the +/-90/spl deg/ phase ambiguity problem and I/Q phase mismatch are also presented.

This paper is the first to combine the joint module-selection and retiming problem with the use of carry-save representation in the optimization of a synchronous circuit. To solve this problem efficiently, we first create a mixed-representation data-flow graph (MFG) by inserting signal representation conversion vertices into the data-flow graph, thus allowing carry-save representation to be freely selected for use. We then identify key properties of an optimal implementation of the MFG that consider the different signal representations as well as the sharing of registers and adders. These properties enable us to formulate the problem as a mixed-integer linear programming problem with cost functions that accurately reflect the true implementation costs of the circuit. Our algorithm, by allowing carry-save representation, can produce a wider range of solutions. In our experiments, our fastest implementation is 27% faster and our smallest implementation is 27% smaller, in comparison with solutions obtained using the previously known joint module-selection and retiming technique.

Arithmetic transformations using carry-save adders have been exploited recently in design automation but existing transformation approaches only optimize combinatorial functions. Most applications need synchronous circuits and it is known that techniques that move the positions of the registers, such as retiming, can significantly reduce the cycle time of a synchronous circuit. However, retiming disregards arithmetic transformations and its power is limited by the circuit topology. This work is the first to exploit carry-save arithmetic transformations together with the moving of the register positions. To enable such transformations, we first propose the use of a new multiple-vector signal representation. Next, we use multiple-vector signal representation as a common guide for all of our simultaneous carry-save arithmetic transformations with the moving of the register positions. Specifically, we propose, operation forward and operation backward carry-save transformations, which are transformations across register boundaries. We also propose operation duplicate and operation merge transformations to exploit the resource sharing and timing trade-offs in the implementation of a multiple-fanout network. Finally, we propose an efficient and effective heuristic that selectively applies a sequence of transformations to optimize the timing and the area of a synchronous circuit. Experimental results show that the proposed techniques significantly out-perform previous approaches.

We discuss the DPASTd algorithm for signal subspace tracking. Our analysis shows that, under a sufficient condition on the step size, the DPASTd algorithm is locally stable even though delayed updating is applied. A pipelined realization of the algorithm and the corresponding systolic architecture are also proposed and a method for reciprocal computation is discussed. We also present simulation results to validate the algorithm.

Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In implementing high-speed circuits, the use of carry-save signal representation is also a powerful technique to optimize the implementation cost and the speed of arithmetic circuits. This paper is the first to combine these two techniques to solve the joint module selection and retiming problem while allowing the use of carry-save representation. To solve this problem efficiently, we first propose a mixed-representation data-flow graph (MFG) that allows signals to be expressed in carry-save representation. We also propose techniques to accurately model the costs associated with different signal representations. In addition, we propose a solution-space pruning technique that significantly reduces the run-time of our algorithm. Our algorithm, by allowing carry-save representation, can produce a wider range of solutions. In our experiments, our fastest implementation is 28% faster and our smallest implementation is 47% smaller, in comparison to solutions obtained using the previously known joint module selection and retiming technique.

In burst-mode data transmission used in GSM and IS-136, rapid acquisition of the symbol timing and the carrier phase from the observation of a short signal-segment is essential. Feedforward timing recovery is well suited for such transmissions due to its rapid acquisition characteristics. For personal mobile communications where low complexity and low power are the major requirements, it is desirable to sample the signal at the lowest possible rate and to have the synchronizer be as simple as possible. In this paper we propose a synchronizer for initial timing and carrier-phase estimation using preambles. The synchronizer needs just two samples per symbol period and it exhibits good performance, even for signals employing small excess bandwidth. These estimations can be obtained directly from the burst detector output. We also show that the synchronizer can be implemented very efficiently.

The application of advanced motion compensation techniques--control grid interpolation (CGI) and overlapped block motion compensation (OBMC)--to video coding systems provides significant performance advantages, terms of compression ratio and visual quality, over traditional block-matching motion compensation. However, the two-dimensional (2-D) interdependence among motion vectors introduced by these compensation frameworks makes the problem of finding rate-distortion optimal motion vectors, computationally prohibitive. Thus, iterative optimization techniques are often used to achieve good compensation performance. While most reported optimization algorithms adopt an approach that uses a block-matching algorithm to obtain an initial estimate and then successively optimize each motion vector, the over-relaxed motion-vector dependency relations often result in considerable performance degradation. In view of this problem, we present a new optimization scheme for dependent motion-vector optimization problems, one based on dynamic programming. Our approach efficiently decomposes 2-D dependency problems into a series of one-dimensional (1-D) dependency problems. We show that a reliable initial estimate of motion vectors can be obtained efficiently by only considering the dependency in the rate term. We also show that at the iterative optimization stage an effective logarithmic search strategy can be used with dynamic programming to reduce the necessary complexity involved in distortion computation. Compared to conventional iterative approaches, our experimental results demonstrate that our algorithm provides superior rate and distortion performance while maintaining reasonable complexity.

We propose an efficient programmable transmit-receive digital filter structure consisting of a pulse shaping filter (PSF) and a cascaded integrator-comb (CIC) filter which is applicable to variable-rate digital communication systems. The CIC structure is a hardware-efficient means of constructing programmable interpolation and decimation filters, but it introduces a large amount of intersymbol interference (ISI). We solve this problem by proposing a filter design method that determines the PSF coefficients such that the cascade of the PSF and CIC filter exhibits the desired frequency response.

Addresses the bit-level optimization of carry-save adder (CSA) arrays when the operands are of unequal wordlength (such as in some datapaths in digital signal processing circuits). We first show that by relaxing the carry-save representation to allow for more than two signals per bit position, we gain flexibility in the bit-level implementation of CSA arrays that can be exploited to achieve a more efficient design. We then propose algorithms to optimize a single adder array at the bit-level. In addition, we proposed a heuristic to optimize a series of adder arrays that might occur in a datapath. We have applied our algorithms to the optimization of high-speed digital FIR filters and have achieved 15% to 30% savings (weighted cost) in the overall filter implementation array in comparison to the standard carry-save implementation.

Motion estimation and compensation is widely used for exploiting temporal correlation within an image sequence. To find motion vectors that lead to high compression, most motion estimation approaches use a source distortion measure, such as mean-square error (MSE) or mean-absolute error (MAE), as a search criterion. When incorporated into a closed-loop motion compensated (MC) transform video coder, these schemes produce noisy motion fields which significantly increase the bit-rates required to represent motion vectors. In view of this problem, this paper presents a rate-distortion optimal motion estimation algorithm. The proposed scheme improves rate performance of the estimated motion field while maintaining the peak signal-to-noise ratio (PSNR) prediction quality of the distortion-based methods, thereby enabling an efficient bit allocation between motion information and transform-coded prediction residuals. For coders in which motion vectors are differentially encoded, the rate-distortion optimization process is formulated as a shortest-path-finding problem. Adopting this framework, we show that the optimal solution for the conventional block-based motion estimation, followed by one-dimensional (1-D) differential coding and Huffman coding, can be obtained by using dynamic programming or the Viterbi algorithm. We propose an effective fast algorithm that closely approximates the optimal performance while requiring considerably less complexity. Our experimental results demonstrate overall gains in the range of 0.3-1.5 dB.

A method for the direction-of-arrival (DOA) estimation of coherent signals is proposed, based on the adaptive version of Pisarenko's harmonic retrieval method. It is known that for the DOA estimation of coherent signals, the computed covariance matrix of the sensor array must be spatially smoothed to preserve its full rank. Adaptive algorithms using the conjugate gradient (CG) methods can take advantage of this pre-processing by incorporating the available smoothed matrix into the algorithm. The proposed algorithm uses the CG algorithm presented previously (see IEEE ICASSP, p.2279-82, 1996) in combination with spatial and temporal smoothing techniques. Our simulations show that the proposed algorithm has a fast convergence rate even when the input signals are coherent. Due to the use of an updated covariance matrix at each time instant, no internal iterations are used as in regular CG methods, resulting in a more efficient algorithm than previously proposed CG methods.

By using a clock rate that is K times the data rate and with interleaved feedback of the output samples, a single expanded digital filter H(z/sup K/) can be made equivalent to a cascade of k identical filters H/sup k/(z) with 1/spl les/k/spl les/K. Whereas this novel pipelining/interleaving (PT) technique can equally be employed for implementing high-performance FIR filters, its main benefit lies in that more efficient high-speed IIR filters become achievable, though their highest possible data rates are still limited by the delays of the critical feedback loops. Hardware architectures and design examples with K=2 are presented to show how the PI technique works for implementing high-speed IIR filters made as the sum of two allpass functions.

This paper discusses the design of a fast algorithm for motion estimation with emphasis on hardware cost considerations, real-time application, network adaptation, and flexibility. To achieve the best trade-off among hardware cost, computational complexity, and distortion performance, we propose a multi-stage pixel-subsampling motion estimation algorithm. The algorithm has a lower hardware cost than Liu's subsampling algorithm and the three-step hierarchical search algorithm (3SHS) in terms of data flow control, I/O bandwidth, and regularity. Its computational complexity is close to that of 3SHS and its distortion performance, which is better than that of Liu's algorithm and 3SHS, is close to that of full search.

At low bit-rates, the coding quality of video is highly dependent on the performance of motion estimation/compensation. One way to obtain reasonable temporal prediction performance is to find an efficient motion coding scheme such that motion information can be compactly represented. To this end, this paper presents a spatial-temporal motion vector coding scheme. While the proposed motion vector coding approach adopts a scheme similar to H.263 with the syntax-based arithmetic coding mode turned on, i.e., spatial differential coding with arithmetic coding, the performance improvements over conventional motion vector coding approaches are made possible by exploiting temporal correlation between motion information of successive frames when choosing probability functions for the arithmetic coder. To obtain the performance gain provided by this coding framework, a rate-distortion motion estimation algorithm that employs delay-decision techniques is developed.

A method for spectral estimation is presented, using the modified conjugate gradient (CG) algorithm. It implements an adaptive version of Pisarenko's harmonic retrieval method, where the estimates are updated sample-by-sample. First, a constrained unit norm CG algorithm is formulated, then it is recast into an unconstrained minimization problem. The resulting algorithms can be extended to solve the generalized eigensystem problem, when the noise covariance matrix is known a priori. It is shown that the proposed algorithms convergence rate is comparable to that of a least-squares type algorithm, while being computationally more efficient. Performance simulations are shown, and comparisons with some existing methods are provided.

A rate-distortion optimal motion estimation algorithm that leads to an efficient bit allocation between inter- and intra-frame information is presented. For coders in which motion vectors are differentially encoded, the rate-distortion optimization process is formulated as a shortest path finding problem. Adopting this framework, we show that the optimal solution for the conventional block-based motion estimation followed by 1-D DPCM and Huffman coding can be obtained by using dynamic programming or the Viterbi algorithm without resorting to an iterative procedure. Since memory and computational requirements for the optimal algorithm increase dramatically with the search range, we propose an effective fast algorithm that closely approximates the optimal performance while requiring considerably less complexity. When used in a hybrid motion compensated (MC) coding system, the proposed scheme outperforms the conventional MSE-optimal motion estimation approach in terms of PSNR performance under a low-bit-rate constraint. Our experimental results demonstrate overall gains in the range of 0.5 to 1.4 dB.

A new logic-timing simulation algorithm, applicable to cycle-based simulation of acyclic combinational logic blocks or synchronous logic designs, is described and implemented. The algorithm is based on evaluating ordered sequences of events, called event-streams, instead of individual events as in a traditional event-driven simulator. This allows very efficient gate evaluations using states unrolling and look-ahead processing. When processing long event-streams, the performance of our simulator can approach that of a compiled-code simulator without the poor instruction-cache behavior of large compiled-code simulations. In addition, the simulator can perform multi-cycle simulations that result in longer event-streams, which enhances the efficiency of gate evaluations. Experimental results show that our simulator runs about four times faster than the Verilog-XL simulator.

While motion fields estimated by maximizing the temporal prediction quality tend to be noisy and demand a large number of bits to encode, finding the motion vectors (MVs) that allow efficient representations requires explicitly considering rate and distortion simultaneously. However, the application of rate-distortion optimization to current variable block size motion compensation (MC) systems is hampered by the fact that MV dependency introduced by the differential coding stage, e.g., the medium differential coding in the advanced prediction mode of the ITU-T standard H.263, makes the rate-distortion (R-D) optimization process extremely difficult. We propose two 1-D differential MV coding frameworks for variable block size MC systems. We show that for one of the proposed differential coding structures the optimal block sizes and the MVs can be jointly obtained by applying dynamic programming (DP) and tree-pruning techniques hierarchically without enumerating all combinations, while a near-optimal solution can be obtained for the other one by adopting a similar optimization procedure with little modification. By comparing the performance of our R-D encoding scheme with that of the H.263 test model TMN5, we find that our approaches achieve 30-60% bit-rate reductions in coding motion vectors, which results in greater than 1 dB gains within a MC hybrid coding environment for most head-and-shoulder videophone sequences under a low-bit-rate constraint.

A generic approach is presented for the design of uniform-band M-channel (M/spl ges/2) perfect-reconstruction FIR filter banks employing linear-phase analysis and synthesis filters. The technique designs on the impulse responses of the analysis filters directly. The design problem is formulated as a quadratic programming problem. The perfect reconstruction feature of the filter bank can either be implicitly enforced through a set of mathematical relationships among the analysis filters' coefficients, or through a set of constraints in the optimization program. The former approach results in a filter bank whose PR (perfect reconstruction) feature's dependency on hardware and software is eliminated or, at least minimized. The criterion for optimality is "least-squares".

An improved algorithm is presented for designing digital filters with coefficients expressed as sums of signed power-of-two (SPT) terms. Our algorithm allocates SPT terms based on minimizing the filter's approximating error using two l/sup /spl infin// norms, one in the time domain and one in the frequency domain. For any specified filter gain, the time complexity of the algorithm is a second-order polynomial in the filter order. Examples show that our improved algorithm is capable of designing filters with better characteristics while using fewer SPT terms.

A new logarithmic block-matching algorithm for motion estimation is proposed. The algorithm exploits the motion correlation of spatially neighboring blocks to reduce the possibility of an inappropriate choice in the search's first stage and thus alleviate the local minimum phenomenon. Compared to existing fast block-matching algorithms, this method achieves significant improvements in both estimation accuracy and performance reliability while maintaining comparable computational complexity and regularity.

A computer algorithm is described that automatically writes optimal programs for the implementation of arbitrary digital filter structures on parallel processors. The algorithm has been adapted particularly for programming a DSP chip with multiple processors arranged in a ring-type topology. The algorithm starts from a netlist describing a desired digital filter structure. It can check all possible timing schedules and all possible distributions of the operations over the parallel processors, taking into account the constraints imposed by the multiprocessor topology and the processors' architecture. The algorithm's output is a set of programs for the parallel processors which causes them to implement the given digital filter.

The standard SPICE dc operating point analysis does not distinguish between stable and unstable operating points. Circuit designers can be misled when an operating point "looks" correct on the basis of dc simulation but turns out to be unobservable once the circuit is breadboarded or fabricated. The algorithm presented herein can identify a large class of unstable operating points, and it has been incorporated into the SPICE dc operating point analysis without compromising analysis speed.>

This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8/spl times/8 blocks. Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation. Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT. The layout has been generated with a 0.8 /spl mu/m CMOS library using the Mentor Graphics GDT tools and measures under 10 mm/sup 2/. Critical path simulation indicates a maximum input sample rate of 100 MHz.>

A technique using Jacobian elliptic functions is given which by removing a previous method's (Powell and Chau, 1991) double-zero constraint, yields improved designs of linear phase IIR filters.>

In this paper, two high-performance implementations of IIR QMF banks for speech coding are proposed. The first implementation involves a perfect reconstruction (PR) QMF bank while the second is a tree-structured filter bank. In contrast to existing implementations of PR QMF banks, our approach does not require the transmission of initial conditions nor the design of synthesis filters which are more complex than their analysis counterparts. In systems with delay constraints, the tree structured IIR QMF bank can be used; a 4-channel scheme shows a low delay of about 1.9 ms (15 samples) at an 8 kHz sampling rate. No existing FIR QMF banks can achieve this low delay. Moreover, the phase distortion of the low-delay filter bank does not appear to affect the perceptual quality of the processed speech signals. Subjective tests were conducted to evaluate the speech quality.>

Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its area requirement below those that are achievable by the traditional tapered CMOS buffers.>

A new approach is presented for the design of three-channel perfect reconstruction (PR) FIR filter banks employing linear-phase analysis and synthesis filters. The approach formulates the design as a quadratic programming problem with nonlinear constraints. The design technique is extendable to M-channel (M/spl ges/2), and this extension is currently under development.>

A programmable general-purpose digital filter IC that employs multiple processing units on a single chip is described. The processors operate in parallel and communicate through on-chip dual-access storage register blocks. The processors are arranged as a ring with the locally shared register blocks between each adjacent pair of processors. It is shown that this ring of processors is capable of realizing a rich variety of filter structures operating at the maximum possible instruction execution rate. Fast real-time processing at video rates is obtained by using a fast hardware multiplier in each processor and by employing a design that permits each processor to simultaneously execute multiplication and addition operations in a single instruction cycle. An advantage of the design is the free passing of data between adjacent processors due to each register block's dual port. A ring of five such processors can be implemented in 2- mu m CMOS technology on a single 7.9 mm*9.2 mm chip operating at data rates up to 40 MHz.>

An optimization technique is presented for the design of multiplierless two-channel linear-phase finite-duration impulse-response (FIR) filter banks. It is shown to yield filter banks with good filtering performance and nearly perfect signal reconstruction. The design employs filters whose coefficients are represented by a canonic signed-digit (CSD) code. When applied to subband image coding this technique provides an easy way to design low-complexity analysis/synthesis filter banks for high-performance codecs. Examples concerning filter design and the application of such filters to subband image coding are given.>

An online multiply-add module that allows high filter sampling rates when used to implement the direct form II second-order filter structure is described. Important characteristics of online arithmetic are that it produces most significant digit first and that its digit cycle time is independent of the data wordlength. These features not only permit high-speed filtering, but also allow the elimination of all nonlinear oscillation in the filter without affecting the sampling rate, and effectively eliminate scaling of the filter's input data. The derivation of the online multiply-add algorithm and its hardware design using a 1.5- mu m CMOS standard cell library are presented. A method for eliminating nonlinear oscillations by increasing the filter's working precision is described.>