In this paper, a novel air-gap-based coaxial Through Silicon Via (TSV) was proposed for on-chip RF interconnect, to fill up the increasing bandwidth gap between the demand and supply according for the 2007 International Technology Roadmap for Semiconductors. Based on earlier work, the expressions of characteristic impedance, attenuation and bandwidth have been proposed. Consequently, we assume an 80 multi-core 3D Network-on-Chip (NoC) system with Binary Phase Shift Keying (BPSK) modulation, to evaluate energy per bit and area per Gbps of the proposed air-gap-based coaxial TSV. The result indicates that the energy dissipation and area consumption of the proposed one are 40~50% and 10% better than the conventional dielectric RF TSV.

In this paper, through-silicon via (TSV) array in the form of one signal and four grounds (1S4G) are proposed to achieve high-frequency vertical connectivity for various three dimensional (3D) IC applications. Self-test method is developed to detect the conductor open and insulator short defects of TSV by capacitive and resistive measuring. Further a recovery mechanism for such a TSV array is introduced to enhance the TSV reliability. Test results will be configured to the TSV chain circuits by the central control logic and be used to determine the connection jumping between signal and redundant TSVs. This way, the failure TSVs could be replaced by the redundant ones. Simulation results demonstrate that the self-test circuit and central control logic could detect and recover the broken TSVs correctly. Moreover, the efficiency and area cost of the recovery mechanism is discussed, and it turns out that in a typical case of 96 signal TSVs, the chip yield could reach 90% with TSV failure rate equal to 5%, in exchange for less than 4% area cost of self-test circuit in the whole TSV area.

In this paper, a novel 3D CMOS nanohybrid technology, 3D CMOL, is introduced to establish FPGA chips. By combining two leading technologies, hybrid CMOS/nanoelectronic circuit (CMOL) and 3D integration, 3D CMOL can provide a feasible and more efficient fabrication/assembly process than the existing 2D CMOL. Furthermore, 3D CMOL FPGA implements circuits in three dimensions so that it can increase the density of the nanodevices and achieve higher performance compared to 2D CMOL and field programmable nanowire interconnect (FPNI). This paper presents the architecture optimization, 3D integration, defect tolerance, and performance evaluation of 3D CMOL FPGA. It is expected that this technology can lead to technology breakthroughs towards the development of the next FPGA generation.

In this paper, a novel CMOS-nano hybrid reconfigurable field-prgrammable gate array architecture (rFPGA) is introduced based on resistive memory (RRAM) devices. Different from the existing crossbar-based CMOS-nano architectures, rFPGA consists of mainly 1T1R RRAM structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel RRAM routing switches are developed to replace the CMOS routing switches to achieve significant density enhancement and power reduction. The simulation results demonstrate that 2-D and 3-D rFPGAs provide at least 2$\times$–3$\times$overall improvement in terms of area with 20% lower power consumption, compared with the corresponding CMOS FPGAs.

In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multi-functional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of delay-power product and signal restoration, while maintaining a similar footprint. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.

In this paper, radio frequency (RF) through-silicon via (TSV) designs and models are proposed to achieve high-frequency vertical connectivity for three dimensional (3D) multi-core and heterogeneous ICs. Specifically, coaxial dielectric and novel air-gap-based TSVs are designed and simulated to reduce signal degradation during RF operations. The simulation results demonstrate that these RF TSVs can provide decay-tolerance frequencies two orders of magnitude higher than simple Cu-plug TSVs. The data rate and energy per bit of the RF TSVs are summarized, providing an important guideline for future 3D high-frequency TSV designs.

This paper develops a novel reconfigurable architecture, CMOS-nanorelay FPGA (cFPGA) by integrating carbon nanorelays with CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2X density and standby power improvement along with a 30% dynamic power reduction as compared with solely CMOS FPGA circuits. This performance improvement is achieved by using 2T1N structures as routing switches: Two CMOS transistors (2T): one for programming purposes, the other for signal transmission; and one nanorelay (1N) as the switching element. These 2T1N structures do not have nanorelays in the signal path, thereby eliminating its large quantum resistance. This is a significant improvement over the conventional CMOS-nanorelay hybrid FPGA circuits. The proposed cFPGA is implemented by using vertical carbon nanotubes that are relatively easier to fabricate as compared with horizontal nanotubes.

This paper introduces a novel CMOS-memristor hybrid reconfigurable architecture, mFPGA. Different from the existing crossbar-based CMOS-memristor architectures, mFPGA mainly consists of lTlM-like structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel CMOS-memristor routing switches are developed to replace the CMOS routing switches to achieve significant density enhancement and power reduction. The simulation results demonstrate that 2D and 3D mFPGAs provide at least a 2X to 3X overall improvement in terms of area reduction, and a 20% lower power consumption, compared with corresponding CMOS FPGA architectures.

In this paper, multilayer graphene nanoribbon (GNR) is proposed as an emerging interconnect solution, which can be integrated with GNR devices to establish a monolithic GNR circuit. Both interconnect resistance and gate capacitance in this circuit are significantly reduced, leading to an RC delay improvement up to 60%. Since the interconnect performance determines the IC operations, this proposed monolithic GNR electronics open new opportunities to establish high-performance nanoscale ICs.

New designs of Redundant Binary full Adders are proposed for redundant binary system, and implemented using 0.18 mum CMOS technology. The proposed full adder designs require low number of transistors and show lower power dissipation and reduced time delay compared to currently available designs. These new designs can be widely used for computer arithmetic units in redundant binary systems. As case studies, two efficient on-line multipliers are implemented using the new full adders, providing improved performance while requiring lower number of transistors.

Carbon nanotube (CNT) bundle is a promising candidate for future on-chip interconnects and electro-thermal applications due to its superior electrical and thermal properties. A realistic CNT bundle is a mixture of single-wall/multi-wall CNTs due to the nature of bottom-up fabrication process. In order to utilize CNT bundle, its current density performance needs to be analyzed considering both types of CNTs. In this paper, compact current density models are introduced for CNTs and mixed CNT bundles considering the influence of diameter and other structural factors. The current density performance estimation based on these models match the recent measurement results. Considering realistic CNT densities and geometries, the mixed bundle shows various levels of improvement over the copper wire counterpart in terms of current density.

In this paper, we introduce a novel reconfigurable architecture, named3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS-nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4.5X footprint reduction compared to traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6X with a small power overhead comparing to the CMOS 2D FPGA architecture.

A novel circuit employing p-type low-temperature poly-Si thin-film transistors is introduced for active matrix-organic light-emitting diode (AM-OLED) circuits to automatically detect short defects and switch to a spare OLED. This design maintains the luminance of the OLED pixel without changing the driving current in the event of defects. Experimental results show that not only is fault tolerance capability obtained during operation, but also a significant amount (around 90%) of power consumption is saved compared with the standard driving circuits.

Chinese remainder theorem based RSA (CRT-RSA) digital signature has important applications in smart cards. Previous CRT-RSA algorithms such as CRT-2 and BOS are susceptible to practical hardware fault attacks. In this paper, a new CRT-RSA algorithm with countermeasures to hardware fault attacks is proposed. To our knowledge, the proposed algorithm is the first that can resist what we call the single-fault adversarial attacks. The proposed algorithm first computes the signature using CRT in a secret algebraic setting, then a set of fault-detection variables are computed to detect possible faults. Lastly, the signature is mapped from the secret algebraic setting to the intended setting. By using a random number and the fault detection variables, every step of the algorithm is protected from hardware faults. The output of the algorithm will be fully randomized in case of faults. The CRT's speed advantages are also maintained. The proposed algorithm is approximately two times as fast as the direct form RSA for the two-prime case, and about four times as fast for the three-prime case

In this paper, various models of carbon nanotube (CNT) and NiSi nanowire are established and used to analyze their performance as future on-chip interconnections. These theoretical studies and simulation results lead to important new findings: NiSi nanowire has superior properties in terms of effective current density and propagation speed compared to Cu and CNT. These properties make NiSi nanowire the most promising candidate for future on-chip interconnections. Bundle CNT also shows promise for long interconnect applications

Projective point elliptic curve cryptography (ECC) involves many look-up table-based field multiplications. In this paper, a novel lookup table sharing scheme is proposed to significantly reduce the number of the field multiplications and number of lookup tables. By requiring much less lookup table generation time, the proposed system offers high-speed performance for hardware realizations. Its application in a reconfigurable PC-FPGA platform is investigated, which can efficiently handle requests for different ECC key length and curves and is useful for many computer network applications

The digital television (DTV) technology becomes widely available and the need for a good interlace-to-progressive conversion (IPC) algorithm becomes more inevitable. In this paper, a new IPC scheme is proposed, which combines several existing techniques and is suitable for hardware implementation. The proposed scheme consists of three components: a spatial linear pre-filter, a motion estimator, and a three stage adaptive recursive (3SAR) filter. The proposed adaptive filter improves the performance of the system without requiring complex hardware design. The computer simulations and real-time FPGA/ASIC implementation demonstrate the efficiency and effectiveness of the proposed scheme in hardware applications

In this paper, a novel passive reduced-order macro-modeling algorithm is proposed for structure dynamics in MEMS systems that are described by discrete models through the use of finite element methods (FEM). In the proposed scheme, the system of equations given by the FEM formulation are converted to state-space form such that the state-space equations are compatible with passive Krylov subspace methods based on congruent transformations. As an example, modeling, simulation, and experimental studies are presented for a Butterfly gyro developed at the Imego Institute. Our simulation results for this example are in very good agreement with previous publications using traditional modeling techniques

In this paper, an efficient immunity method is proposed for two-prime RSA cryptosystem against hardware fault attack. The proposed system has more immunity than the previous system and is targeted for FPGA implementation. For the 32-bit signing case, the proposed method is 15% faster than the previous design while requiring only 70% of the hardware resource.

In this paper, a new architecture of the redundant residue number system (RRNS) based quasi-chaotic coding is proposed for the secure telecommunication systems and networks. In the proposed architecture, a number of modulo operations required by the existing designs are replaced by binary coding operations to simplify the design. Also, a moduli selection method and a residue-to-binary converter with error-correction capability are proposed to further improve the efficiency of the design specifically for FPGA implementation. The proposed architecture is implemented and tested using Matlab and Xilinx FPGA hardware. The results show that compared to the existing design, the proposed design requires only 80% of the hardware resources while maintaining the same speed. The power consumption is also reduced by 25%.

We propose a new modulo arithmetic theorem to decompose the base of modulo operations. This new theorem has been used to reduce further the modulo size of the modified CRT (Chinese remainder theorem) for general moduli sets. Furthermore, we have applied the modulo decomposition technique and the modulo improved CRT to derive a R/B (residue-to-binary) converter algorithm for a newly found three-moduli set, M={2/sup n/-1,2/sup n/, 2/sup n-1/-1}. In comparison to the modified CRT, the improved CRT can cut the modulo size by half and reduce the length of the modulo operator in terms of 36%.

A high-speed parallel residue-to-binary converter is proposed for the moduli set S/sup k/={2/sup m/-1, 2/sup 2(0)m/+1, 2/sup 2(l)m/+1, L, 2.