This paper presents the first dysarthric voice conversion SoC, which can translate stroke patients' voice into more intelligible and clearer speech in real time. The SoC is composed of a RISC-V MPU and a compact DNN engine with a single 16-bit multiply-accumulator, which improves 12x performance and > 100x energy efficiency, and has been implemented in 40nm CMOS. The silicon area is 0.68×0.79mm2, and the measured power is 18.4mW for converting 3-sec dysarthric voice within 0.5 sec (at 200MHz and 0.8V) and 4.8mW for conversion < 1 sec (at 100MHz and 0.6V).

During systems-on-a-chip (SoC) integration, silicon intellectual properties (IPs) are generally regarded as blockages to long interconnections that connect different IPs. With this constraint, conventional designs are forced to place those repeaters that drive long interconnections outside the IP. These designs either lead to a longer interconnection distance requiring more repeaters or result in a longer signal delay, since the interconnection wire is not appropriately segmented by the repeaters. To solve these problems, we designed the IPs such that designers can embed the repeaters in the IP for the SoC integration. In other words, it allows the cross-IP interconnections to be routed over the IP using repeaters inserted in the IP. The design concept, physical implementation, and application examples of the embedded repeaters are described in this brief. Experimental results show that the proposed design will not only make the floor plan of the SoC easier but will also improve the signal delay and the power consumption of the long interconnection circuits.

This paper presents a complexity-effective HHT IP for embedded real-time applications. The proposed HHT improves the original empirical mode decomposition (EMD) to reduce the interferences between signal components with filtering, similar to that in the wavelet transform. The IMF and residue signals are compacted to reduce computation and storage. Multirate Hilbert spectral analysis (HSA) is performed to further reduce computations. A prototype of an embedded HHT analyzer has been built to demonstrate the effectiveness.

This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, several circuits are proposed on top of a delay chain to adapt the timing control of power switches to process variations. Experimental results show that the proposed design is able to track process variation such that the surge current and the wakeup time are both kept to expectation in all process corners.

Power gating is an effective technique for reducing leakage power in deep submicron CMOS technology. Microarchitectural techniques for power gating of functional units have been developed by detecting suitable idle regions and turning them off to reduce leakage energy consumption; however, wakeup of functional units is needed when instructions are ready for execution such that wakeup overhead is naturally incurred. This study presents time-based power gating with reference pre-wakeup (PGRP), a novel predictive strategy that detects suitable idle periods for power gating and then enables pre-wakeup of needed functional units for avoiding wakeup overhead. The key insight is that most wakeups are repeated due to program locality. Thus, the pre-wakeup predictor learns the wakeup events and selects which prior branch instruction can provide early wakeup (wakeup patterns are visible); these information are then used to adequately prepare available functional units for instruction execution. Simulation results with benchmarks from SPEC2000 applications show that substantial leakage energy reduction with negligible performance degradation (0.38% on average) is worthwhile.

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the size of sleep transistors for the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop. We also present efficient heurists for minimizing the sizes of sleep transistors. Our experimental results are very exciting.

In a 0.13 /spl mu/m design environment, we design two level converters to convert signals from 0.6V and 0.8V to 1.2V, respectively, to fulfill the needs of a multi-island dual-VDD CMOS SOC. Heuristic sizing guidelines are proposed to achieve better conversion speed and lower conversion energy for both level converters.

Traditionally, technology mapping is done by first partitioning a circuit into a forest of trees. Each individual tree is then mapped using dynamic programming. The links among the mappings of different trees are provided via propagating the essential mapping information along multiple fanout branches. While this approach may achieve optimality within each tree, the overall result is compromised from the very first treatment of fanouts. In this article, we propose a new scheme that greatly improves technology mapping. Instead of a forest of trees, we partition the circuit into a set of maximal super-gates (MSGs). These are used to transform the original circuit into trees. We then apply the dynamic programming technique to the trees and allow duplication of gates in the mapping of each individual MSG. Experimental results on ISCAS'85 benchmarks show that our approach delivers an average of 20.6% reduction in delay with only a 9.5% increase on area.

Dynamic programmable logic arrays (PLAs) which are built of the nor-nor structure, have been very popular in high performance design because of their high-speed and predictable routing delay. However, the nor-nor structure incurs high switching activity in product lines and, thus, results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the nand functionality on top of the nor structure, thus, lowering the switching activities in the product lines, as well as power consumption. Since there are many candidates for super product lines, we have developed a computer-aided design (CAD) algorithm based on the maximum weighted matching to find the optimal solution. We have performed experiments on a large set of Microelectronics Center of North Carolina (MCNC) benchmark circuits. The post simulation results show significant reduction in power consumption. Among the experimental circuits, circuit alu3 has the highest power saving 62.9% with the delay overhead 5.4%, and circuit newpla2 has the lowest power saving with delay overhead 22.7%. In addition, circuit in4 improves the delay with 5.7%. On the average, the power consumption can be saved 55.8% and the delay overhead is merely 3.3% for 25 circuits.

In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus lowering the switching activities in the product lines as well as power consumption. Since there are many candidates for super product lines, we have developed a CAD algorithm based on the maximum weighted matching to find optimal solution. The post simulation results show significant reduction in power consumption. On the average, the power consumption can be saved 58.9% and the delay overhead is merely 1.6% for 18 circuits.

This paper proposes a flexible hardware solution and the associated energy-aware IP core design for computing the variable-length discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) required in the MPEG4 shape-adaptive DCT/IDCT (SA-DCT/IDCT). The proposed IP core has been developed based on the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware. To achieve good performance both in area and speed, we optimize the proposed IP core both in the algorithmic computational complexity and hardware complexity. Furthermore, the proposed IP core possesses the feature of energy-aware design flexibility. The simulation shows that the proposed design has 44% energy reduction at the price of 0.3-dB signal quality degradation for the image compression applications. The implementation results show that the proposed IP core costs about 3100 gates along with 16 words (1 word = 16 bits) of memory, which can achieve the real-time processing of the texture coding in MPEG4 SP@L3 and ACE@L2 CODEC system for the CIF format video at 30 frames/s with 4:2:0 color format.

A power-aware SNR progressive DCT/IDCT IP core design for multimedia transform coding is proposed. The proposed IP core possesses the feature of power-aware design flexibility, allowing the trade-off of lower power consumption with less demand of data precision in developing its instruction library. Relationships of energy reduction and data quality degradation in the examples of both JPEG still images and MPEG4 video sequences have been analyzed. Since the proposed IP core is developed based on the concept of programmable processors, we can select a DCT/IDCT firmware library of different precisions of cosine coefficients according to the accuracy requirement of various applications. This design has been realized based on a 0.35-/spl mu/m CMOS technology and costs about 2175 gates with 8 words of RAM, which can achieve real-time processing of the texture coding in an MPEG4 SP@L3 codec system for CIF video at 30 frames per second (fps).

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous research focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this correspondence, we present cell-based layout techniques that make the approach feasible. We first propose a new block layout style and a placement strategy to support the voltage scaling with conventional standard cell libraries. Then, we propose a new cell layout style with built-in multiple supply rails so that gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques maintain good power benefit while introducing moderate layout overhead.

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous research focused on determining the voltage level for each gate and ascertaining the power-saving capability of the approach via logic-level power estimation. In this paper, we present cell-based layout techniques that make the approach feasible. We first propose a new block layout style and a placement strategy to support the voltage scaling with conventional standard cell libraries. Then we propose a new cell layout style with built-in multiple supply rails so that gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques maintain good power benefit while introducing moderate layout overhead.

Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several research attentions. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. In this paper, we propose a pattern oriented power modeling for improved technology mapping. We first perform a profitability study using the complete pattern to pattern transition data organized in tabular form. Then, we propose a probability-based, pattern oriented technology mapping method. Empirical results on benchmark circuits demonstrate the proposed method delivered an average of 13% power reduction compared to the traditional mapping method.

The advent of portable and high-density devices has made power consumption a critical design concern.In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget.We first use a maximum-weighted independent set formulation for voltage reduction on non-critical part of the circuit.Then, we use a minimum-weighted separator set formulation to do gate sizing and integrate the sizing procedure with a voltage scaling procedure to enhance power saving on the whole circuit.The proposed methods are evaluated using the MCNC benchmark circuits.and an average of 19.12% power reduction over the circuits having only one supply voltage has been achieved.

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous researches focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this paper, we present the layout techniques that feasiblize the approach in cell-based design environment. A new block layout style is proposed to support the voltage scaling with conventional standard cell libraries. The block layout can be automatically generated via a simulated annealing based placement algorithm. In addition, we propose a new cell layout style with built-in multiple supply rails. Using the cell layout, gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques produce very promising results.

Rectilinear placement is an important process for mixed macro block/standard cells design due to frequent presence of preplaced macro blocks. A prevailing solution to this problem is to divide the rectilinear region into rectangular sub-regions and partition cells into these sub-regions before applying standard placement algorithms. For such a strategy to work, the partitioning objective must closely correlate with the global routing objective. In this paper, we propose a new method to integrate global routing with partitioning. The salient features of our approach consist of (1) a new edge cost model and its computation using an incremental assignment technique; (2) a resistive network analogy for net cost modeling and a randomized algorithm for resistance computation; (3) a robust partitioning framework that combines the ideas of (1) and (2). Also, a dynamic strategy is proposed to evaluate the performance of the algorithm. Our method has been tested on several benchmark circuits and displayed excellent results in terms of both wire length and routability.

Flow-based method has been successful in producing high-quality circuit clusterings at the expense of long running time. In this paper, we explore the tradeoff between clustering quality and running time. We show that optimum flow distribution, which is a key concept of flow-based clustering, may not be indispensable if some compromise of the clustering result is allowed. By releasing the demand for optimum flow distribution, significant speedup can be achieved. Our result provides an alternative to applications where fast yet reasonably good clustering is required. >

Recently, Johnson et al. [1989] presented an excellent comparison of simulated annealing and Kernighan-Lin algorithms. However, their test beds were limited to random and geometric graphs. We present a complete evaluation by adding real circuitry into the test beds. A two-level partitioning algorithm called the primal-dual algorithm is also incorporated for comparison. We show that at least 500 runs are necessary to demonstrate the performance of the Fiduccia-Mattheyses algorithm, whereas traditional way of evaluation tends to underestimate. Nevertheless, our new results show that for two-way partitioning on real circuits, the primal-dual algorithm is, in general, a better choice than both the Fiduccia-Mattheyses algorithm and the simulated annealing algorithm. This conclusion is more likely to hold when the primal-dual algorithm is switched to a simpler mode.>

We present a new clustering metric, based on a random graph model and a ratio cut concept. The minimization of the proposed clustering cost can be transformed to a uniform multicommodity flow problem by adding artificial weight functions, which can be solved by a multicommodity flow-based algorithm with high complexity. We devise a probabilistic flow injection approach which drastically reduces the complexity of the flow-based algorithm. Experimental results show that this algorithm generates promising results with respect to the proposed metric.>

Multiple-way partitioning is an important extension of two-way partitioning as it provides a more natural and direct model for many partitioning applications. In this paper, we discuss several objective functions derived from such an extension and propose an iterative improvement algorithm to solve the multiple-way partitioning problem. The algorithm proceeds in three phases. The first phase employs a recursive ratio-cut scheme to group highly connected subcircuits into clusters. The second phase performs iterative improvement on the clustered circuit using a Dew net-based move model and a Primal-Dual refinement procedure. The third phase is the same as the second phase except that the iterative improvement is done on the original circuit. Experiments show good results in all tested cases.>

A block-oriented programmable design with switching network interconnect is proposed for fast turn-around, low manufacturing cost, and layout-independent high-speed systems. We introduce the architecture and investigate the constraints and properties originated from the architecture. We show that routability is the most crucial concern for a successful design, and propose objective functions as well as algorithms for switching network optimization. The mapping for the circuits is performed by partitioning, placement, and routing using a maximum matching method. The integration of the whole system demonstrates excellent results in terms of circuit usage.>

Circuit clustering, which plays a fundamental role in hierarchical designs, is discussed. Identifying strongly connected components in the circuits can significantly reduce the complexity of the design and improve the performance of the design process. However, there has not been a clear objective function for circuit clustering. A clustering metric based on the random graph model and the ratio cust concept is presented. A probabilistic, multicommodity flow based algorithm is proposed and tested under the clustering metric. Experimental results show that this algorithm generates promising results with respect to the proposed metric. Extensions and directions for future work are also proposed.>

This paper presents a discussion of methods to solve multiple way partitioning problems under three different objective functions.A multicommodity flow fzeatmertt is proposed for partitioning without a size wmstrain~and an iterative improvement algorithm is proposed for partitioning with a size comt.rstint.This algoriti incorporates a top-down clustering technique to deal with the local minima problems in common heuristics, a novel multi-pin net model to capture the contributory moves, and a Primal-Dual iteration to enhance the iterative improvement.Experiments show good results in all tested cases over the algorithm proposal in [12].Also, the effect of different objective functions is manifested through numerical tabulation.