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Gerhard Zimmermann

dblp:z/GZimmermann · DBLP profile ↗
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9ranked-venue papers
2as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 2 first-authorSoftware engineering, systems software and programming languages · 1Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 97% Integrated circuit design · 3%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.021988
A New Area and Shape Function Estimation Technique for VLSI Layouts · DAC 1988
Spider, a chip planner for ISL technology · DAC 1984
Electronic design automation › design data management
design database
0.011989
An Object-Oriented Datamodel for the VLSI Design System PLAYOUT · DAC 1989
Electronic design automation
design data management
0.011989
An Object-Oriented Datamodel for the VLSI Design System PLAYOUT · DAC 1989
Electronic design automation › design methodology
VLSI design system
0.011989
An Object-Oriented Datamodel for the VLSI Design System PLAYOUT · DAC 1989
Electronic design automation › physical design › design planning
chip planning
0.011984
Spider, a chip planner for ISL technology · DAC 1984
Electronic design automation
high-level synthesis
0.011979
The MIMOLA design system a computer aided digital processor design method · DAC 1979

Methods — techniques the papers use, named apart from their topics

object-oriented modeling · 0.0MIMOLA design system · 0.0
YearPublicationVenuePosition
1997 Application of a Generator-Based Software Development Method Supporting Model Reuse
Joachim Altmeyer, Jan Peter Riegel, Bernd Schürmann, Martin Schütze, Gerhard Zimmermann
CAiSE5
1992 Three-phase chip planning - an improved top-down chip planning strategy
abstract
An improved top-down chip planning method that reduces the effects of differences of the estimated shapes in the floorplan and the final layouts are introduced. In a fully recursive approach, each cell is planned several times with different presumptions. Bottom-up adjustment steps use refined shape functions instead of rigid dimensions. Although such bottom-up adjustment steps were performed, the general direction is top-down. The convergence of the procedure can be ensured. The method is described in detail and some experimental results are provided. Several real large test designs (the largest example has nearly 300000 standard cells) have been performed with the PLAYOUT design system to compare the pure top-down approach with the new method.>
Bernd Schürmann, Joachim Altmeyer, Gerhard Zimmermann
ICCAD3
1991 A Genetic Algorithm for Global Improvement of Macrocell Layouts
abstract
The result of many floorplanning algorithms is a placement of macrocells. A novel technique for the improvement of a given placement is presented which is based on the optimization of the channel densities by refining the cell positions. The authors introduce a distance function for each channel representing the channel width. This width can be altered by shifting adjacent cells along each other by an offset. They present an optimization to find offsets for adjacent cells which lead to a minimal area demand of the total layout. The method is based on a genetic algorithm, an iterative improvement procedure. Results are presented.>
Klaus Glasmacher, A. Hess, Gerhard Zimmermann
ICCD3
1991 Efficient Production System Execution on the PESA Architecture
Franz Schreiner, Gerhard Zimmermann
ICPP (1)2
1989 An Object-Oriented Datamodel for the VLSI Design System PLAYOUT
abstract
A complete datamodel for an integrated VLSI design system is developed in a stepwise manner. This datamodel introduces a unified view of all design domains and hierarchy levels that result in a considerable simplification of the communication among the design tools. We defined five basic objects: cell, interface, contents, instance and configuration for high level description of all design data. The model also covers views, types, alternatives, versions and the design history. In particular our handling of the configuration demonstrates reasonable response times, due to the strict avoidance of redundant information and the storage of complex objects. This datamodel can be directly used for the implementation of an efficient object-oriented design database.
Ernst Siepmann, Gerhard Zimmermann
DAC2
1988 A New Area and Shape Function Estimation Technique for VLSI Layouts
Gerhard Zimmermann
DAC1
1987 PESA I-A Parallel Architecture for Production Systems
Franz Schreiner, Gerhard Zimmermann
ICPP2
1984 Spider, a chip planner for ISL technology
Prakash Rao, R. Ramnarayan, Gerhard Zimmermann
DAC3
1979 The MIMOLA design system a computer aided digital processor design method
Gerhard Zimmermann
DAC1