GPUs which serve as graphic-oriented computation platform are now gradually used to solve a range of compute-intensive and data-parallel scientific computing problems which can be perfectly parallelized for performance speedups. Particularly, GPUs have recently become popular to host the encryption/decryption algorithms due to its high-throughput computing capability. However, the security issues of moving the cryptographic algorithms onto GPUs have not been studied adequately. Consequently, with absence of any protection strategy, the potential vulnerabilities of GPUs to side-channel attacks may expose the confidential information with high risk. In this paper, we propose a Profiling-Assisted Correlation-based Side-Channel Attack (pacSCA) to demonstrate that ignoring security issues and naively moving security services onto GPUs can offer adversaries fatal vulnerabilities to thieve critical information. The results show that the proposed SCA can rebuild the secure key of the AES-128 algorithm in less than 6 seconds, revealing the urgency of protecting GPUs against side-channel threats.

Current heterogeneous CPU-GPU architectures integrate general purpose CPUs and highly thread-level parallelized GPUs (Graphic Processing Units) in the same die. The contention in shared resources between CPU and GPU, such as the last level cache (LLC), interconnection network and DRAM, may degrade both CPU and GPU performance. Our experimental results show that GPU applications tend to have much more power than CPU applications to compete for the shared resources in LLC and on-chip network, and therefore make CPU suffer from more performance loss. To reduce the GPU's negative impact on CPU performance, we propose a simple yet effective method based on probability to control the LLC replacement policy for reducing the CPU's inter-core conflict misses caused by GPU without significantly impacting GPU performance. In addition, we develop two strategies to combine the probability based method for the LLC and an existing technique called virtual channel partition (VCP) for the interconnection network to further improve the CPU performance. The first strategy statically uses an empirically pre-determined probability value associated with VCP, which can improve the CPU performance by 26% on average, but degrades GPU performance by 5%. The second strategy uses a sampling method to monitor the network congestion and dynamically adjust the probability value used, which can improve the CPU performance by 24%, and only have 1 or 2% performance overhead on GPU applications.

General-purpose graphics processing units (GPGPUs) usually employ a huge register file (RF) to support massive multithreading, which however, is also responsible for a large fraction of GPGPU's total power. In this paper, we propose three RF drowsy policies and evaluate their effectiveness on leakage energy reduction. In the first drowsy policy called immediate sleep (Drowsy-IS), registers keep staying in the drowsy mode unless they are accessed, which are then put into the drowsy mode again immediately to minimize the leakage energy consumption. The second policy named temporary awake (Drowsy-TA) holds the registers in the normal (i.e. active) mode for a certain period after being accessed to wait for the next access. The registers are placed into the drowsy mode until that period expires without any access activity. Finally, we propose an adaptive policy named Drowsy-RI which identifies the re-access interval for each register at run-time and lets registers wait for the predicted intervals before putting them into the drowsy mode. The experimental results show that compared to the baseline RF, Drowsy-IS achieves 91.7% RF leakage energy reduction on average at the cost of 4.4% performance degradation. Drowsy-TA leads to negligible performance overhead, and 82.8% leakage energy reduction. By balancing the energy saving and the performance overhead, Drowsy-RI saves more RF leakage energy (87.3%) than Drowsy-TA and achieves less performance degradation (2.7%) than Drowsy-IS.

The capability of GPUs to accelerate general-purpose applications that can be parallelized into massive number of threads makes it promising to apply GPUs to real-time applications as well, where high throughput and intensive computation are also needed. However, due to the different architecture and programming model of GPUs, the worst-case execution time (WCET) analysis methods and techniques designed for CPUs cannot be used directly to estimate the WCET of GPUs. In this work, based on the analysis of the architecture and dynamic behavior of GPUs, we propose a WCET timing model and analyzer based on a predictable GPU warp scheduling policy to enable the WCET estimation on GPUs.

Heterogeneous multicore processors with integrated CPU and GPU cores on the same chip pose new challenges and opportunities for time-predictable resources sharing, which is crucial for hard real-time and safety-critical systems. The shared last-level cache (LLC) can result in a large number of interferences between CPU and GPU (Graphic Processing Units) LLC accesses with diverse patterns and characteristics, thus impacting the performance and time predictability of both CPUs and GPUs. In this paper, we explore cache partitioning, locking and a combination of them to make the LLC time-predictable for integrated CPU-GPUs while achieving high performance. By evaluating these LLC management approaches, we are able to provide real-time systems developers recommendations on the most effective time-predictable LLC designs for heterogeneous CPU-GPU multicore processors.

Graphics Processing Units (GPUs) have great potential to improve the performance and energy efficiency for data-parallel real-time applications. However, it is very difficult to compute worst-case execution time (WCET) for current GPUs that are design for improving the average-case throughput, not for time predictability. In this paper, we propose a warp-based load/store reordering mechanism to improve the time predictability of GPU data caching without incurring much performance overhead. This mechanism can be used in conjunction with dynamic warp scheduling to achieve better performance than a pure round-robin based scheduling while enabling accurate static timing analysis to bound the worst-case GPU L1 data cache misses.

Cache memories have been introduced in recent generations of Graphics Processing Units (GPUs) to benefit general-purpose computing on GPUs (GPGPUs). In this work, we analyze the memory access patterns of GPGPU applications and propose a cost-effective profiling-based method to identify the data accesses that should bypass the L1 data cache to improve performance. The evaluation indicates that the proposed L1 cache bypassing can improve the GPU performance by 13.8% on average.

Cache memories are widely used in microprocessors to improve the average-case memory performance. However, they are harmful to time predictability, and thus may not be desirable for real-time systems. In this paper, we make simple hardware extensions of a regular cache to implement the performance enhancement guaranteed cache (PEG-C). The PEG-C is totally controlled by hardware, which can automatically improve the average-case performance of real-time software with guaranteed and enhanced worst-case performance.

Recent Graphics Processing Units (GPUs) have employed cache memories to boost performance. However, cache memories are well known to be harmful to time predictability for CPUs. For high-performance real-time systems using GPUs, it remains unknown whether or not cache memories should be employed. In this paper, we quantitatively compare the performance for GPUs with and without caches, and find that GPUs without the cache actually lead to better average-case performance, with higher time predictability. However, we also study a profiling-based cache bypassing method, which can use the L1 data cache more efficiently to achieve better average-case performance than that without the cache. Therefore, it seems still beneficial to employ caches for real-time computing on GPUs.

In this paper, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. Since SPM can reduce the access frequency to the cache, we find it is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated Vdd (HDG) technique, which can adaptively exploit both short and long idle intervals to minimize leakage energy with insignificant performance overhead.

In this paper, we first propose a static analysis approach to estimate the maximum value of the worst-case latency of all possible communications in a Chip Multi-Processor (CMP) with a 2D-Mesh Network-on-Chip (NoC), which is called the Worst-case Inter-core Communication Latency (WICL). Then the Hop-based Priority scheduling approach is proposed for a 2D-Mesh NoC to improve its WICL. Our experimental results indicate that the Hop-based Priority (HP) scheduling can reduce the WICL by 50% in average for various network sizes compared with that of the FIFO scheduling.

In this paper, we present a dynamic-compiler-directed approach which adaptively configures CPU's function units at runtime. It is based on Jikes RVM's dynamic optimizing compiler and is designed to achieve higher energy efficiency. We describe the implementation to support compiler-controlled adaptive FU and the cost/benefit heuristic of selecting optimization targets to save energy. Our experiment results indicate that this approach achieves about 40% to 65% ALU energy reduction, and reduces the total energy consumption by 6.3% to 14%.

Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET) accurately and safely. In this paper, we develop a WCET analysis approach to consider the effects of static NUCA caches on WCET, and compare the WCET of the real-time applications in different topologies of the static NUCA caches. The experimental results demonstrate that the static NUCA cache can improve the worst-case performance of the real-time applications in the multicore processor as compared to the cache with uniform access time.

In this paper, we propose a Performance Enhancement Guaranteed Cache (PEG-C) to ensure performance benefit in the worst case while achieving as good average-case performance as a regular hardware-controlled cache. Our experiments indicate that with a small number of preloaded data and a simple hardware extension, the PEG-C can guarantee performance enhancement in the worst case while achieving the same average-case performance as a regular cache.

Cache memories, while useful for improving the average-case performance for general-purpose applications, are not suitable for real-time systems due to the time unpredictability. In this paper, we propose a Performance Enhancement Guaranteed Cache (PEG-C) to ensure performance improvement in the worst case while achieving as good average-case performance as a regular hardware-controlled cache. We design and evaluate an instruction PEG-C as a proof-of-concept. Our experiments indicate that with a small number of preloaded instructions, the PEG instruction cache can achieve the same performanceas a regular instruction cache, and outperform cache locking significantly.

This paper first proposes the concept of architectural time predictability, which separates the time variation due to hardware architectural/microarchitectural design from that caused by software. We then propose a new metric - standard deviation of clock cycles per instruction (CPI), to measure architectural time predictability. Our experiments confirm that standard deviation of CPI is an effective metric to evaluate and compare architectural time predictability for different processors.

Time predictability and performance are usually two conflicting goals. In this paper, we propose an on-chip hybrid SRAM architecture by putting a small cache and a small ScratchPad Memory (SPM) together. Our evaluation indicates that with the equivalent total on-chip storage size, the time predictability of most hybrid architectures is better than that of caches only, and the performance of most hybrid architectures is better than that of SPMs only. Moreover, we find that for some benchmarks, the SPM and the cache can cooperate effectively in the hybrid architectures to achieve performance superior to the cache-only architecture.

In this paper, we study a compiler-based approach to reducing the instruction SPM leakage energy efficiently, which can also minimize the performance overhead. Our evaluation indicates that the compiler-based approach is superior to periodical or bank-based methods. On average, the compiler-based method can reduce the SPM leakage energy by nearly 89.82%, with only 0.25% performance overhead.

This paper studies the Scratch-Pad Memory (SPM) allocation for a hybrid SPM and cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and/or energy efficiency. To benefit hard real-time systems, this paper proposes and evaluates four SPM allocation strategies to reduce the worst-case execution time (WCET) for hybrid SPM-caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can maximally reduce the WCET with minimum or even positive impact on the average-case execution time (ACET).

Graphics Processing Units (GPUs) have become a popular choice for general-purpose high-performance computing. Encryption and decryption algorithms such as the Advanced Encryption Standard (AES) have been implemented on GPUs to gain significant speedup. However, the security of the GPU architecture is not well studied, making it potentially risky to offload sensitive computation to GPUs. In this paper, we will introduce our ongoing work to improve GPU security against Denial of Service (DoS) attacks.

In modern multicore processor architectures, caches are widely used to shorten the speed gap between the processor and the memory. However, caches are time unpredictable, especially the shared L2 cache used by different cores in a multicore processor. This paper studies several time-predictable scratchpad memory (SPM) based architectures for multicore processors. We propose the dynamic memory objects allocation-based partition, the static allocation-based partition, and the static allocation-based priority L2 SPM strategy to retain the characteristic of time predictability of SPMs while trying to maximize the performance and energy efficiency. Our experimental results indicate the strengths and weaknesses of each proposed architecture and allocation method, which offers interesting memory design options to enable real-time multicore computing.

As multicore processors are increasingly adopted in industry, it has become a great challenge to accurately bound the worst-case execution time (WCET) for real-time systems running on multicore chips. This is particularly true because of the inter-thread interferences in accessing shared resources on multicores, such as shared L2 caches, which can significantly affect the performance but are very difficult to be estimated statically. This article proposes an approach to analyzing WCET for multicore processors with shared L2 instruction caches by using a model checking based method. We model each concurrent real-time thread, including the inter-thread cache interferences with a PROMELA process, and derive the WCET by using a binary search algorithm. To reduce the state explosion problem, we propose several techniques for reducing the memory consumption by exploiting domain-specific information. Our experiments indicate that compared to the static analysis technique based on extended ILP (integer linear programming), our approach improves the tightness of WCET estimation by more than 31.1% for the benchmarks we studied. However, due to the inherent complexity of multicore timing analysis and the state explosion problem, the model checking based approach currently can only work with small real-time kernels for dual-core processors.

This paper presents the course development activities on multicore programming at the Electrical and Computer Engineering Department of Virginia Commonwealth University. As multicore processors have become the main stream computing platform, it becomes a necessity to teach undergraduate on programming for multicore processors. This paper gives details information about the multicore programming course developed at VCU, including the course modules and a brief introduction of the labs.

Inter-thread interferences in shared caches can significantly affect the worst-case execution time (WCET) of real-time tasks running on multi-core chips. In this paper, we study three multicore-aware code positioning methods to reduce the inter-core L2 cache interferences between co-running real-time threads. One strategy focuses on decreasing the longest WCET among the co-running threads, and two other methods aim at achieving fairness in terms of the amount or percentage of WCET reduction among co-running threads. Our experiments indicate that the proposed multicore-aware code positioning approaches not only improve the worst-case performance of the real-time threads, but also make tradeoffs between efficiency and fairness for threads running on multi-core platforms.

Unified L2 caches can lead to runtime interferences between instructions and data, making it very hard, if not impossible, to perform timing analysis for real-time systems. This paper proposes a priority cache to achieve both time predictability and high performance for real-time systems. The priority cache allows both the instruction and data streams to share the aggregate L2 cache; however, instructions and data cannot replace each other to enable independent instruction cache and data cache timing analyses. Our performance evaluation shows that the instruction priority cache outperforms separate L2 caches, both of which can achieve time predictability. On average, the number of execution cycles of the instruction priority cache is only 1.1% more than that of a unified L2 cache.

Estimating and optimizing worst-case execution time (WCET) is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can enhance both the average-case and worst-case performance; however, the improvement on the worst-case execution time is rather limited and inefficient. This paper studies a loop-based instruction prefetching approach, which can exploit the program control-flow information to intelligently prefetch instructions that are most likely needed. Our evaluation indicates that the loop-based instruction prefetching outperforms the Next-N-Line prefetching in both the worst-case and the average-case performance for real-time applications.

With the advance of computer and communication technologies, wireless sensor networks (WSNs) are increasingly used in many aspects of our daily life. However, since the battery lifetime of WSN nodes is restricted, the WSN lifetime is also limited. Therefore, it is crucial to determine this limited lifetime in advance for preventing service interruptions in critical applications. This paper proposes a feasible static analysis approach to estimate the worst-case lifetime of a WSN. Assuming known routes with a given sensor network topology and S-MAC as the underlying MAC protocol, we statically estimate the lifetime of each sensor node with a fixed initial energy budget. These estimations are then compared with the results obtained through simulation which run with the same energy budget on each node. Experimental results of our research on TinyOS applications indicate that our approach can safely and accurately estimate the worst-case lifetime of WSNs. To the best of our knowledge, our work is the first one to estimate the worst-case lifetime of WSNs through static analysis method.

As a successful programming language, Java has extended its application from general-purpose systems to embedded, real-time systems. However, some of Java's excellent features, like automatic memory management and dynamic compilation, bring indeterminism to the execution time of real-time Java programs. In this paper, we propose several multi-core approaches to remove or at least reduce the unpredictability inside of Java Virtual Machine (JVM). Our goal is to retain high performance competitive to dynamic compilation and, at the same time, obtain better time predictability for JVM. Also, we study pre-compilation techniques to utilize second core more efficiently. Furthermore, we develop Pre-optimization on Another Core (PoAC) scheme to replace the Adaptive Optimization System (AOS) in Jikes JVM, which is very sensitive to execution time variation and impacts time predictability greatly. The experimental results indicate that our approaches are able to reach high performance while greatly reduce execution time variation of Java applications.

In a multicore processor, different cores typically share the last level cache, and threads running on different cores may interfere with each other in accessing the shared cache. Therefore, multicore WCET (worst case execution time) analyzer must be able to safely and accurately estimate the worst case interthread cache interferences, which is not supported by current WCET analysis techniques that mainly focus on analyzing uniprocessors. This paper proposes a novel approach to analyzing the worst case cache interferences and bounding the WCET for threads running on multicore processors with shared direct mapped L2 instruction caches. We propose to use an extended ILP (integer linear programming) to model all the possible interthread cache conflicts, based on which we can accurately calculate the worst case interthread cache interferences and derive the WCET. Compared to a recently proposed multicore static analysis technique based on control flow information alone, this approach improves the tightness of WCET estimation by 13.7% on average.

Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Machines (JVM), however, the binary code is typically written into the data cache, and then is loaded into the instruction cache through the shared L2 cache or memory, which is not efficient in terms of both time and energy. In this paper, we study three hardware-based code caching strategies to write and read the dynamically generated code faster and more energy-efficiently. Our experimental results indicate that writing code directly into the instruction cache can improve the performance of a variety of Java applications by 9.6% on average, and up to 42.9%. Also, the overall energy dissipation of these Java programs can be reduced by 6% on average.

Drowsy cache has been proved as an efficient technique to reduce cache leakage energy. However, current drowsy cache control policies generally suffer from performance loss and are not adaptive to different program behaviors. In this paper, we study adaptive drowsy cache control for Java applications, where just-in-time (JIT) compiler and runtime information can be used to make accurate decision on drowsy cache control. We first explore the impact of different phases of Java applications on the timing behavior of cache usage. Then we propose several techniques to adaptively control drowsy cache to reduce energy consumption with minimal impact on performance. Our experiments show that the adaptive drowsy control by exploiting the phase information can reduce the performance loss without impacting the energy saving, which is especially useful during the garbage collection.

Java applications rely on just-in-time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java virtual machines (JVM), however, the binary code is typically written into the data cache, and then is loaded into the instruction cache through the shared L2 cache or memory, which is not efficient. In this paper, we study different efficient code caching strategies to write and read the dynamically generated code faster. Our experimental results indicate that writing code directly into the instruction cache can improve the performance of Java application by up to 42.9%, with 9.6% on average.

Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately obtain the worst-case execution time (WCET) of applications running on multi-core platforms, which is very challenging due to the possible runtime inter-core interferences in using shared resources such as the shared L2 caches. As the first step toward time-predictable multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst- case shared L2 instruction cache misses by considering inter-thread instruction conflicts. Also, the WCET of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

It is well known that a large fraction of variables are short-lived. This paper proposes a novel approach to exploiting this fact to reduce the register pressure for pipelined processors with data-forwarding network. The idea is that the compiler can allocate virtual registers (i.e., place holders to identify dependences among instructions) to short-lived variables, which do not need to be stored to physical storage locations. As a result, real registers (i.e., physically existed registers) can be reserved for long-lived variables for mitigating the register pressure and decreasing the register spills, leading to performance improvement. In this paper, we develop the architectural and compiler support for exploiting virtual registers for statically scheduled processors. Our experimental results show that virtual registers are very effective at reducing the register spills, which, in many cases, can achieve the performance close to the processor with twice number of real registers. Our results also indicate that, for some applications, using 24 virtual, in addition to 8 real registers, can attain even higher performance than that of 16 real without any virtual registers.

Time predictability is one of the most important design considerations for real-time systems. In this article, we study the impact of instruction prefetching on the worst-case performance of instruction caches. We extend the static cache simulation technique to model and compute the worst-case instruction cache performance with prefetching. The evaluation results show that instruction prefetching can benefit both the average-case and worst-case performance; however, the degree of the worst-case performance improvement due to instruction prefetching is less than that of the average-case performance. As a result, the time variation of computing is increased by instruction prefetching. Also, our experimental results indicate that the prefetching distance can significantly impact the worst-case performance of instruction caches with instruction prefetching. Specifically, when the prefetching distance is equal to the L1 miss penalty, the worst-case execution time with instruction prefetching is minimized.

We propose a multi-resolution framework inspired by human visual search for general object detection. Different resolutions are represented using a coarse-to-fine feature hierarchy. During detection, the lower resolution features are initially used to reject the majority of negative windows at relatively low cost, leaving a relatively small number of windows to be processed in higher resolutions. This enables the use of computationally more expensive higher resolution features to achieve high detection accuracy. We applied this framework on Histograms of Oriented Gradient (HOG) features for object detection. Our multi-resolution detector produced better performance for pedestrian detection than state-of-the-art methods (Dalal and Triggs, 2005), and was faster during both training and testing. Testing our method on motorbikes and cars from the VOC database revealed similar improvements in both speed and accuracy, suggesting that our approach is suitable for realtime general object detection applications.

Instruction prefetching is an effective technique to reduce the instruction cache miss latency for improving the average-case performance. For real-time systems, however, the use of instruction prefetching will only besuitable if a reasonably tight worst-case performance of programs using instruction prefetching can be predicted. This paper presents an approach to modeling and computing the worst-case instruction cache performance with prefetching. Our experimental results indicate that instruction prefetching can benefit both the average-case and worst-case performance; however, the degree of the worst-case performance improvement due to instruction prefetching is less than that of the average-case performance, thus leading to increased time variation for real-time computing. Also, we find that the prefetching distance can significantly impact the worst-case performance analysis with instruction prefetching. Particularly, when the prefetching distance is equal to the L1 miss penalty, the worst-case execution time with instruction prefetching is minimized (i.e., optimal).

With the scaling of technology, leakage energy will become the dominant source of energy consumption. Besides cache memories, branch predictors are among the largest on-chip array structures and consume nontrivial leakage energy. This paper proposes two cost-effective loop-based strategies to reduce the branch predictor leakage without impacting prediction accuracy or performance. The loop-based approaches exploit the fact that loops usually only contain a small number of instructions and, hence, even fewer branch instructions while taking a significant fraction of the execution time. Consequently, all the nonactive entries of branch predictors can be placed into the low leakage mode during the loop execution in order to reduce leakage energy. Compiler and circuit supports are discussed to implement the proposed leakage-reduction strategies. Compared to the recently proposed decay-based approach, our experimental results show that the loop-based approach can extract 16.2% more dead time of the branch predictor, on average, leading to more leakage energy savings without impacting the branch prediction accuracy and performance.

The mobile computing device market has been growing rapidly. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in the future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present three compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. Integer ALU (IALU) components operating with multiple supply voltages are designed to provide different low-energy versions that possess different operational latencies. The goal of the first technique explored is to maximize the number of operations mapped to IALU components with the lowest energy consumption without extending the schedule length. We also consider a variant of this technique that saves more energy at the cost of some performance loss. The second technique uses two leakage-control mechanisms to reduce leakage energy consumption when no operations are scheduled in the component. Our evaluation of these two approaches, using fifteen benchmarks, shows that based on the number and duration of slacks, the availability of low-energy functional units and the relative magnitude of leakage and dynamic energy, either leakage or dynamic energy consumption, will provide more energy gains. Finally, we provide a unified energy-optimization strategy that integrates both dynamic and leakage energy-reduction schemes. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit-level simulation. Our results show that the unified scheme generates better results than using either of dynamic and leakage energy-reduction techniques independently.

We combine local texture features (PCA-SIFT), global features (shape context), and spatial features within a single multi-layer AdaBoost model of object class recognition. The first layer selects PCA-SIFT and shape context features and combines the two feature types to form a strong classifier. Although previous approaches have used either feature type to train an AdaBoost model, our approach is the first to combine these complementary sources of information into a single feature pool and to use Adaboost to select those features most important for class recognition. The second layer adds to these local and global descriptions information about the spatial relationships between features. Through comparisons to the training sample, we first find the most prominent local features in Layer I, then capture the spatial relationships between these features in Layer 2. Rather than discarding this spatial information, we therefore use it to improve the strength of our classifier. We compared our method to (R. Fergus et al., 2003, A. Opelt et al., 2004, J. Thureson et al., 2004) and in all cases our approach outperformed these previous methods using a popular benchmark for object class recognition (R. Fergus et al., 2003). ROC equal error rates approached 99%. We also tested our method using a dataset of images that better equates the complexity between object and non-object images, and again found that our approach outperforms previous methods.

With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely used in reliability-sensitive environments, it becomes increasingly important to develop cost-effective techniques to improve the processor reliability against soft errors. This paper focuses on studying the register file immunity against soft errors since modern processors typically employ a large number of registers, which are accessed very frequently. As a result, soft errors occurred in registers can easily propagate to functional units or the memory system, leading to silent data error (SDC) or system crash.To develop cost-effective techniques to fight soft errors for embedded processors, the first step is to understand the register file susceptibility to soft errors and its impact on the system reliability accurately. Toward this goal, this paper proposes the concept of register vulnerability factor (RVF) to characterize the probability that register transient errors can escape the register file and thus potentially impact the system reliability. Built upon the RVF concept, we then propose two cost-effective compiler-guided techniques to improve the register file reliability by lowering the RVF value. Our experiments indicate that on average, the RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly while protecting register files against transient errors.

To investigate how top-down (TD) and bottom-up (BU) information is weighted in the guidance of human search behavior, we manipulated the proportions of BU and TD components in a saliency-based model. The model is biologically plausible and implements an artificial retina and a neuronal population code. The BU component is based on feature- contrast. The TD component is defined by a feature-template match to a stored target representation. We compared the model’s behavior at differ- ent mixtures of TD and BU components to the eye movement behavior of human observers performing the identical search task. We found that a purely TD model provides a much closer match to human behavior than any mixture model using BU information. Only when biological con- straints are removed (e.g., eliminating the retina) did a BU/TD mixture model begin to approximate human behavior.

We present a computational model of human eye movements in an ob- ject class detection task. The model combines state-of-the-art computer vision object class detection methods (SIFT features trained using Ad- aBoost) with a biologically plausible model of human eye movement to produce a sequence of simulated fixations, culminating with the acqui- sition of a target. We validated the model by comparing its behavior to the behavior of human observers performing the identical object class detection task (looking for a teddy bear among visually complex non- target objects). We found considerable agreement between the model and human data in multiple eye movement measures, including number of fixations, cumulative probability of fixating the target, and scanpath distance.

Soft error conscious cache design has become increasingly crucial for reliable computing. The widely used ECC or parity-based integrity checking techniques have only limited capability in error detection and correction, while incurring nontrivial penalty in area or performance. The N modular redundancy (NMR) scheme is too costly for processors with stringent cost constraints. This paper proposes a cost-effective solution to enhance data reliability significantly with minimum impact on performance. The idea is to add a small fully associative cache to store the replica of every write to the L1 data cache. Due to data locality and its full associativity, the replication cache can be kept small while providing replicas for a significant fraction of read hits in L1, which can be used to enhance data integrity against soft errors. Our experiments show that a replication cache with eight blocks can provide replicas for 97.3 percent of read hits in L1 on average. Moreover, compared with the recently proposed in-cache replication schemes, the replication cache is more energy efficient, while improving the data integrity against soft errors significantly.

Silicon technology advances have made it possible to pack millions of transistors---switching at high clock speeds---on a single chip. While these advances bring unprecedented performance to electronic products, they also pose difficult power/energy consumption problems. For example, large number of transistors in dense on-chip cache memories consume significant static (leakage) power even if the cache is not used by the current computation. While previous compiler research studied code and data restructuring for improving data cache performance, to our knowledge, there exists no compiler-based study that targets data cache leakage power consumption. In this paper, we present code restructuring techniques for array-based and pointer-intensive applications for reducing data cache leakage energy consumption. The idea is to let the compiler analyze the application code and insert instructions that turn off cache lines that keep variables not used by the current computation. This turning-off does not destroy contents of a cache line and waking up the cache line (when it is accessed later) does not incur much overhead. Due to inherent data locality in applications, we find that, at a given time, only a small portion of the data cache needs to be active; the remaining part can be placed into a leakage-saving mode (state); i.e., they can be turned off. Our experimental results indicate that the proposed compiler-based strategy reduces the cache energy consumption significantly. We also demonstrate how different compiler optimizations can increase the effectiveness of our strategy.

As feature sizes shrink, leakage energy reduction has become increasingly important, especially for cache memories. Recent research in drowsy instruction cache shows that the leakage energy of the instruction cache can be significantly reduced with little performance degradation by exploiting the instruction spatial locality at the cache sub-bank level[5]. The performance penalty due to the sub-bank wake-up latency is dramatically reduced by using a prediction buffer to pre-activate the next sub-bank at runtime. However, consulting the prediction buffer at every cache access consumes non-trivial dynamical energy, which can compromise the overall energy savings substantially. This paper proposes a static approach to capture the sub-bank transition behavior at link time and to pre-activate the instruction cache sub-bank at runtime according to the compiler-directed hints. We also propose a hybrid approach to exploit both the static and dynamic information for reducing the performance penalty further with little dynamic energy overhead. Our experiments reveal that the static approach is very successful in capturing the sub-bank transition behavior for reducing the performance penalty and it also reduces 38.2% more leakage energy than the hardware-based approach, taking the dynamic energy overhead into account. Moreover, our results show that the hybrid approach is the best strategy for the drowsy instruction cache to balance leakage energy reduction and performance.

Leakage energy consumption is becoming an important design consideration with the scaling of technology. Besides caches, branch predictors are among the largest on-chip array structures and consume non-trivial leakage energy. This paper proposes two loop-based strategies to reduce the branch predictor leakage without impacting prediction accuracy, which is crucial for achieving high performance. The loop-based approaches exploit the fact that loops usually only contain a small number of instructions and hence fewer branch instructions. Consequently, all the non-active entries of branch predictors can be placed into the low leakage mode during the loop execution for leakage energy savings. Compilers can annotate this information and pass it to the processor for reducing leakage at runtime. Compared to the recently-proposed decay-based approach, our experimental results show that the loop-based approach can extract 16.2% more branch predictor idleness on average, leading to more leakage energy savings without impacting the branch prediction accuracy and performance.

Soft error conscious cache design is a necessity for reliable computing. ECC or parity-based integrity checking technique in use today either compromises performance for reliability or vice versa, and the N modular redundancy (NMR) scheme is too costly for microprocessors and applications with stringent cost constraint. This paper proposes a novel and cost-effective solution to enhance data reliability with minimum impact on performance. The idea is to add a small fully-associative cache to store the replica(s) of every write to the L1 data cache. The replicas can be used to detect and correct soft errors. The replication cache can also be used to increase performance by reducing the L1 data cache miss rate. Our experiments show that more than 97% read hits of the L1 data cache can find replicas available in a replication cache of 8 blocks.

Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms. We also evaluate the sensitivity of these optimizations to different high-level compiler transformations, energy parameters, and soft errors.

The importance of L1 data caches makes their performance, power consumption, and data integrity characteristics extremely critical in embedded systems design. We examine these issues in the context of a mechanism that tries to enhance data cache reliability by replicating cache lines (blocks) in active use. When replicating data cache lines, it is important to not evict other lines that may be needed or to not incur very high power consumption. We evaluate the tradeoffs between these three goals (reliability, energy, and performance) by modulating two important parameters, namely, the hot-block threshold and the dead-block threshold. We show that having a hot-block threshold in the range of 10-1000 cycles can provide good reliability characteristics, without compromising on performance or power. At the same time, our results indicate that one could use aggressive dead-block thresholds to provide leakage power savings without compromising on the performance and reliability characteristics. The results from this paper can be used to design power, performance, and reliability enhanced cache architectures.

As datasets processed by embedded processors increase in size and complexity, the management of higher levels of memory hierarchy (e.g., caches) is becoming an important issue. A major limitation of most of the cache locality optimization techniques proposed by previous research is that they handle a single procedure at a time. This prevents compilers from capturing the data access interactions between procedures and may result in poor performance. In this paper, we look at loop and data transformations from a different angle and use them in an interprocedural optimization framework. Employing the call graph representation of a given application, the proposed technique visits each node of this graph twice and uses loop and data transformations in a systematic way for optimizing array layouts whole program wide. Our experimental results show that this interprocedural locality optimization strategy is much more effective than the previous locality-based techniques that handle each procedure in isolation.

We present a compiler-oriented strategy to reduce the memory system energy consumption due to instruction accesses and increase performance by exploiting scratch pad memories. Scratch pad memories (SPMs) are alternatives to conventional cache memories in embedded computing. These small on-chip memories, like caches, provide fast and low-power access to data and instructions; but, they differ from caches in that their contents are managed by software instead of hardware. Our compiler framework keeps the most frequently used instructions in SPM and dynamically changes the contents of the SPM as the (instruction) working set of the application changes.

Processor caches already play a critical role in the performance of today's computer systems. At the same time, the data integrity of words coming out of the caches can have serious consequences on the ability of a program to execute correctly, or even to proceed. The integrity checks need to be performed in a time-sensitive manner to not slow down the execution when there are no errors as in the common case, and should not excessively increase the power budget of the caches which is already high. ECC and parity-based protection techniques in use today fall at either extremes in terms of compromising one criteria for another, i.e., reliability for performance or vice-versa. This paper proposes a novel solution to this problem by allowing in-cache replication, wherein reliability can be enhanced without excessively slowing down cache accesses or requiring significant area cost increases. The mechanism is fairly power efficient in comparison to other alternatives as well. In particular, the solution replicates data that is in active use within the cache itself while evicting those that may not be needed in the near future. Our experiments show that a large fraction of the data read from the cache have replicas available with this optimization.

Silicon technology advances have made it possible to pack millions of transistors --- switching at high clock speeds --- on a single chip. While these advances bring unprecedented performance to electronic products, they pose difficult power/energy consumption problems. For example, large number of transistors in dense on-chip cache memories consume significant static (leakage) power even if the cache is not used by the current computation. While previous compiler research studied code and data restructuring for improving data cache performance, to our knowledge, there is no compiler-based study that targets data cache leakage power consumption. In this paper, we present code restructuring techniques for array-based and pointer-intensive applications for reducing data cache energy consumption. The idea is to let the compiler to analyze the code and insert instructions that turn off cache lines that keep variables not used by the current computation. This turning off does not destroy contents of a cache line, and waking up the cache line incurs very little overhead. Due to data locality, we find that at a given time only a small portion of the data cache needs to be active; the remaining part can be placed into a leakage-saving mode (state); i.e., they can be turned off. Our preliminary results indicate that the proposed strategy reduces the cache energy consumption significantly. We also show that several compiler optimizations increase the effectiveness of our strategy.

Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.

The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule stacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.