Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed so far for various MRAM technologies. The last part of this article gives some perspectives on this hot topic.

Due to high switching activities in test mode, circuit power consumption is higher than its functional operation. Large switching in the circuit during launch-to-capture cycles not only negatively impacts circuit performance causing overkill, but could also burn tester probes during wafer test due to the excessive current they must drive. It is necessary to develop a quick and effective method for evaluating each pattern, identifing high-power patterns considering functional and tester probes' current limits and making the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in the power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

We present a fast power analysis flow called Power MAX in this paper. Power MAX is specially devised for power evaluation of test vectors. It has the capability of power calculation and peak current identification for each test cycle. This cycle-by-cycle power and current monitoring ensures the power-safety of test vectors before they are loaded to testers. Power MAX is layout-aware, thus able to pinpoint hotspots as well. The entire power analysis flow is seamlessly integrated into test vector simulation. Power MAX fills the gap of test power analysis flows that achieves both efficiency and accuracy. We believe our flow is the first attempt to address vector-based power evaluation problem especially for test mode. Results on industrial hard macros show that Power MAX provides high power-integrity sign-off accuracy with low CPU runtime.

Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.

Freezing scan cell outputs can block transitions to the combinational components thus reduce shift power. The extra logic introduces area overhead, reduces timing margin and increases power in capture mode. This paper proposes a partial gating flow that calculates instance toggling probability to identify power sensitive cells. The toggling rate reduction tendency is demonstrated to be useful in estimating how much extra logic is needed to achieve a desired shift power reduction rate for a design. To ensure power safety across entire test session, the toggling rate metric is enhanced to consider the effect of capture power increase. A complementary pair of weights can adjust the power change in shift and capture modes, thus achieve an overall balanced power safety. The toggling probability metric along with the proposed flow provide a flexibility that benefits various practical power requirements when considering current limits of both circuit and tester.

Large switching during launch-to-capture cycle in delay test not only negatively impacts circuit performance causing overkill, but could also burn tester probes due to the excessive current they must drive. It is necessary to develop a quick and effective method to evaluate each pattern, identify high-power ones considering functional and tester probes' current limit and make the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS not only exhibits higher performance in coverage but also does not require as much extra power as predicted, especially in terms of peak power. These facts may represent convincing arguments for its wider use and development.